Patents by Inventor Yuming Bai
Yuming Bai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10453953Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: GrantFiled: December 21, 2016Date of Patent: October 22, 2019Assignee: VISHAY-SILICONIXInventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
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Publication number: 20170104096Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
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Publication number: 20150331438Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: July 28, 2015Publication date: November 19, 2015Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 9093359Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: July 28, 2015Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8928138Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: May 13, 2010Date of Patent: January 6, 2015Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8883580Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: GrantFiled: December 27, 2012Date of Patent: November 11, 2014Assignee: Vishay-SiliconixInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
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Patent number: 8823098Abstract: The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.Type: GrantFiled: March 7, 2012Date of Patent: September 2, 2014Assignee: Wuxi Versine Semiconductor Corp. Ltd.Inventors: Qin Huang, Yuming Bai
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Publication number: 20140235023Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: ApplicationFiled: December 27, 2012Publication date: August 21, 2014Applicant: VISHAY-SILICONIXInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
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Patent number: 8604541Abstract: This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.Type: GrantFiled: April 6, 2012Date of Patent: December 10, 2013Assignee: Wuxi Versine Semiconductor Corp. Ltd.Inventors: Qin Huang, Yuming Bai, Yang Gao
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Patent number: 8471381Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: June 25, 2013Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8368126Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: GrantFiled: April 7, 2008Date of Patent: February 5, 2013Assignee: Vishay-SiliconixInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-In Chen
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Publication number: 20120256254Abstract: This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.Type: ApplicationFiled: April 6, 2012Publication date: October 11, 2012Inventors: Qin HUANG, Yuming BAI, Yang GAO
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Publication number: 20120248534Abstract: The invention discloses a manufacture method and structure of a power transistor, which comprises a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode; wherein the two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the surface of the two gate units; the upper electrode covers; the surface of the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.Type: ApplicationFiled: March 7, 2012Publication date: October 4, 2012Inventors: Qin HUANG, Yuming Bai
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Patent number: 8183629Abstract: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.Type: GrantFiled: March 18, 2008Date of Patent: May 22, 2012Assignee: Vishay-SiliconixInventors: Deva Pattanayak, Jason (Jianhai) Qi, Yuming Bai, Kam-Hong Lui, Ronald Wong
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Publication number: 20110254084Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: ApplicationFiled: March 2, 2011Publication date: October 20, 2011Applicant: VISHAY-SILICONIXInventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
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Publication number: 20100219519Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 7704836Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: GrantFiled: March 31, 2008Date of Patent: April 27, 2010Assignee: Siliconix incorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
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Publication number: 20100019316Abstract: A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: ApplicationFiled: September 29, 2009Publication date: January 28, 2010Applicant: Siliconix incorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
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Patent number: 7557409Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: GrantFiled: January 26, 2007Date of Patent: July 7, 2009Assignee: Siliconix IncorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
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Publication number: 20090050960Abstract: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.Type: ApplicationFiled: March 18, 2008Publication date: February 26, 2009Applicant: VISHAY-SILICONIXInventors: Deva Pattanayak, Jason (Jianhai) Qi, Yuming Bai, Kam-Hong Lui, Ronald Wong