Patents by Inventor Yu-Ming Li

Yu-Ming Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12165722
    Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a high-voltage (HV) driver, a global HV power switch configured to generate a HV power signal, and a HV power switch coupled between the global HV switch and the HV driver. The HV power switch is configured to, responsive to the HV power signal, output power and ground signals, each of the power signal and the ground signal having first and second voltage levels, and the HV driver is configured to output a HV activation signal to a column of the bank of NVM devices responsive to the power signal and the ground signal.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gu-Huan Li, Chen-Ming Hung, Yu-Der Chih
  • Publication number: 20240379873
    Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Hung Wei LI, Yu-Ming LIN, Mauricio MANFRINI, Kuo-Chang CHIANG, Sai-Hooi YEONG
  • Patent number: 12139465
    Abstract: The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole, and organic optoelectronic devices comprising the same.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: November 12, 2024
    Assignee: RAYNERGY TEK INCORPORATION
    Inventors: Yu-Tang Hsiao, Chia-Hao Lee, Chuang-Yi Liao, Chun-Chieh Lee, Chia-Hua Li, Hsiuan-Ling Ho, Yi-Ming Chang
  • Patent number: 12133474
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 12125920
    Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung Wei Li, Yu-Ming Lin, Mauricio Manfrini, Kuo-Chang Chiang, Sai-Hooi Yeong
  • Publication number: 20240317675
    Abstract: An electrochromic composition includes an oxidizable compound, a reducible compound, and a solvent. The oxidizable compound includes wherein each R2 is independently —N(R1)2, —OR1, or —R1, and R1 is C1-3 alkyl group. The reducible compound has a chemical structure of and each R3 is independently C4-12 alkyl group, —OCnH2n+1, and n=0˜7.
    Type: Application
    Filed: December 22, 2023
    Publication date: September 26, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Guey-Sheng LIOU, Chyi-Ming LEU, Jheng-Ying LI, Hsiang-Jui CHEN, Yu Jen SHAO, Min Hsiu TU, Hou Lin LI
  • Publication number: 20240304394
    Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.
    Type: Application
    Filed: January 12, 2024
    Publication date: September 12, 2024
    Inventors: Yu-Peng Chung, Chia-Wei Li, Wen Cheng Hsu, En-Ming Chen, Che-Chih Tsao
  • Patent number: 12087579
    Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin
  • Patent number: 12057275
    Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces and through holes that pass through the conductive pads. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: August 6, 2024
    Inventors: Yu-Peng Chung, Chia-Wei Li, Wen Cheng Hsu, En-Ming Chen, Che-Chih Tsao
  • Publication number: 20230325641
    Abstract: The invention provides a light source optimization apparatus including a storage apparatus and a processor. The storage apparatus stores a plurality of modules. The processor is coupled to the storage apparatus and configured to execute the plurality of modules. The plurality of modules include a critical pattern module and a light source optimization module. The critical pattern module retrieves critical pattern data. The light source optimization module executes an ant colony optimization (ACO) algorithm according to a preset parameter to adjust an initial light source image to generate an output light source image, and the initial light source image corresponds to the critical pattern data.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Tung-Yu Wu, Chun-Yen Liao, Tsung-Wei Lin, Chun-Sheng Wu, Chao-Yi Huang, Yu Ming Li, Hung-Fei Kuo
  • Publication number: 20230282482
    Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
    Type: Application
    Filed: June 4, 2022
    Publication date: September 7, 2023
    Inventors: Tsung-Han Shen, Kevin Chang, Yu-Ming Li, Chih-Hsiang Fan, Yi-Ting Wang, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Publication number: 20120194289
    Abstract: A frequency modulation feedback system applied to an actuation device composed of a carrier and a drive unit for driving the carrier. The frequency modulation feedback system includes: a feedback device for reading a feedback signal of the carrier and transmitting the feedback signal; a control section for receiving and reading the feedback signal to drive the drive unit; a passage, the feedback signal being transmitted from the feedback device via the passage to the control section; and a modulation device for modulating the waveform of the transmitted feedback signal. After the feedback device reads the feedback signal, the feedback device first transmits the feedback signal to the modulation device for the modulation device to change the waveform of the feedback signal. Then the feedback signal is transmitted via the passage to the control section for reading.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Inventor: Yu-Ming Li