Abstract: Low Density Parity Check (LDPC) decoder circuitry in which memory resources are realized as single-port memory. The decoder circuitry includes a single port memory for storing log-likelihood ratio (LLR) estimates of input node data states for individual rows of a parity check matrix. The decoder circuitry also includes multiple instances of single-port column sum memories, which store updated LLR estimates for each input node. In each case, the memory resources include logic circuitry that executes at least one write cycle and one read cycle to the memory within each decoder cycle. Because the decoder cycle time is much longer than the necessary memory cycle time, particularly in LDPC decoding, data can be written to and read from single-port memory resources in ample time for the decoding operation.

Abstract: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

Abstract: A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.