Patents by Inventor Yun-An Yeh

Yun-An Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8717365
    Abstract: Data is received that describes a polyline having a first endpoint, a second endpoint, and a plurality of intermediate vertices, each of the intermediate vertices lying between the first endpoint and the second endpoint. An estimation line segment is drawn between the first endpoint and the second endpoint. An intermediate vertex is identifies as a pivot vertex from the plurality of intermediate vertices that is a greatest distance from the estimation line segment. A flatness ratio is calculated by dividing a distance of the pivot vertex from the estimation line segment by a length of the estimation line segment In a computer, the flatness ratio is compared to a predetermined threshold value. If the flatness ratio does not exceed the predetermined threshold value, the intermediate vertices are discarded, thereby modifying the polyline.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 6, 2014
    Assignee: Verizon Patent and Licensing Inc.
    Inventor: Ching-Yun Yeh
  • Patent number: 8509116
    Abstract: A computer-implemented method receives a list of polygonal vertices associated with multiple polygons located in proximity to one another in a two-dimensional region and analyzes the polygonal vertices. The method automatically generates, based on the analysis, a polygonal hull that encloses the multiple polygons such that a line segment connecting any two polygonal vertices of the multiple polygons falls completely inside the generated polygonal hull. The multiple polygons may correspond to a two-dimensional geographic region. The computer-implemented method may be used for geographic regional segmentation.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: August 13, 2013
    Assignee: Verizon Patent and Licensing, Inc.
    Inventors: Ching-Yun Yeh, Robert Funk, Kumar Annamraju
  • Patent number: 8284698
    Abstract: A computer-implemented method receives a set of data regarding a layout of a network, where the data specifies the interconnection of linear facilities and specifies at least one network point that is disconnected from the network. The computer-implemented method further determines a closest one of the linear facilities to the at least one network point based on the set of data and shifts the at least one network point to connect the at least one network point to the network based on a distance between a vertex associated with the closest one of the linear facilities and the at least one network point. The computer-implemented method also shifts the closest one of the linear facilities to connect the at least one network point in the network based on a distance associated with a linear projection from the at least one network point to the closest one of the linear facilities.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: October 9, 2012
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Ching-Yun Yeh, Robert Funk, Kumar Annamraju
  • Publication number: 20120089333
    Abstract: A computer receives a set of Cartesian data and a set of geodetic data relating to a geographic area. A set of control points is generated, each control point being associated with a coordinate expressed in terms of latitude and longitude, and with a corresponding point in the Cartesian data. A plurality of sets of Cartesian coordinates is determined for each of the control points, each of the sets of Cartesian coordinates for one of the control points corresponding to a Cartesian system. A deviation is determined for a combination that includes a control point and a Cartesian system, the deviation being a difference between coordinates for the point in the Cartesian data and the set of Cartesian coordinates for the control point. For each set of Cartesian coordinates associated with the Cartesian system that is included in the combination, but further associated with a control point not in the combination, the set of Cartesian coordinates is modified according to the deviation.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 12, 2012
    Inventors: Ching-Yun Yeh, Kumar Annamraju, Anurag X. Singh, Nageswara R. Tanuku
  • Publication number: 20120032962
    Abstract: Data is received that describes a polyline having a first endpoint, a second endpoint, and a plurality of intermediate vertices, each of the intermediate vertices lying between the first endpoint and the second endpoint. An estimation line segment is drawn between the first endpoint and the second endpoint. An intermediate vertex is identifies as a pivot vertex from the plurality of intermediate vertices that is a greatest distance from the estimation line segment. A flatness ratio is calculated by dividing a distance of the pivot vertex from the estimation line segment by a length of the estimation line segment In a computer, the flatness ratio is compared to a predetermined threshold value. If the flatness ratio does not exceed the predetermined threshold value, the intermediate vertices are discarded, thereby modifying the polyline.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: Verizon Patent and Licensing Inc.
    Inventor: Ching-Yun Yeh
  • Publication number: 20100315977
    Abstract: A computer-implemented method receives a list of polygonal vertices associated with multiple polygons located in proximity to one another in a two-dimensional region and analyzes the polygonal vertices. The method automatically generates, based on the analysis, a polygonal hull that encloses the multiple polygons such that a line segment connecting any two polygonal vertices of the multiple polygons falls completely inside the generated polygonal hull. The multiple polygons may correspond to a two-dimensional geographic region. The computer-implemented method may be used for geographic regional segmentation.
    Type: Application
    Filed: August 26, 2010
    Publication date: December 16, 2010
    Applicant: VERIZON PATENT AND LICENSING INC.
    Inventors: Ching-Yun YEH, Robert FUNK, Kumar ANNAMRAJU
  • Patent number: 7813301
    Abstract: A computer-implemented method receives a list of polygonal vertices associated with multiple polygons located in proximity to one another in a two-dimensional region and analyzes the polygonal vertices. The method automatically generates, based on the analysis, a polygonal hull that encloses the multiple polygons such that a line segment connecting any two polygonal vertices of the multiple polygons falls completely inside the generated polygonal hull. The multiple polygons may correspond to a two-dimensional geographic region. The computer-implemented method may be used for geographic regional segmentation.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: October 12, 2010
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Ching-Yun Yeh, Robert Funk, Kumar Annamraju
  • Publication number: 20090303903
    Abstract: A computer-implemented method receives a set of data regarding a layout of a network, where the data specifies the interconnection of linear facilities and specifies at least one network point that is disconnected from the network. The computer-implemented method further determines a closest one of the linear facilities to the at least one network point based on the set of data and shifts the at least one network point to connect the at least one network point to the network based on a distance between a vertex associated with the closest one of the linear facilities and the at least one network point. The computer-implemented method also shifts the closest one of the linear facilities to connect the at least one network point in the network based on a distance associated with a linear projection from the at least one network point to the closest one of the linear facilities.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 10, 2009
    Applicants: VERIZON DATA SERVICES LLC, VERIZON NORTH INC.
    Inventors: Ching-Yun Yeh, Robert Funk, Kumar Annamraju
  • Publication number: 20090279453
    Abstract: A computer-implemented method receives a list of polygonal vertices associated with multiple polygons located in proximity to one another in a two-dimensional region and analyzes the polygonal vertices. The method automatically generates, based on the analysis, a polygonal hull that encloses the multiple polygons such that a line segment connecting any two polygonal vertices of the multiple polygons falls completely inside the generated polygonal hull. The multiple polygons may correspond to a two-dimensional geographic region. The computer-implemented method may be used for geographic regional segmentation.
    Type: Application
    Filed: May 8, 2008
    Publication date: November 12, 2009
    Applicants: Verizon Data Services LLC, Verizon North Inc.
    Inventors: Ching-Yun YEH, Robert FUNK, Kumar ANNAMRAJU
  • Patent number: 7356632
    Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 8, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Bi-Yun Yeh, Jiin Lai, Sheng-Chung Wu
  • Patent number: 7325125
    Abstract: A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the memory space and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: January 29, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Bi-Yun Yeh, Shu-Tzu Wang, Heng-Chen Ho
  • Publication number: 20060184757
    Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 17, 2006
    Inventors: Bi-Yun Yeh, Jiin Lai, Sheng-Chung Wu
  • Patent number: 7082489
    Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: July 25, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Bi-Yun Yeh, Jiin Lai, Sheng-Chung Wu
  • Publication number: 20050289304
    Abstract: A control chip for controlling and accessing an external memory module. The control chip comprises a terminal module and a decision unit. The terminal module is coupled to the external memory module through a memory bus for selectively matching the impedance of the memory bus. The decision unit is coupled to the terminal module and determines whether to turn on the terminal module according to a terminal signal, a dynamic select signal, and a read signal.
    Type: Application
    Filed: March 11, 2005
    Publication date: December 29, 2005
    Inventor: Bi-Yun Yeh
  • Publication number: 20040240206
    Abstract: A laser pointer with external power is disclosed, which comprises a laser generator, an interface for external-power connection, and a current limiting resistor. The laser generator is to generate laser beams. The interface for external-power connection is coupled to a power supply device for providing power to the laser generator. Besides, the power switch is to control whether the power should be conducted to the laser generator. Also, the current limiting resistor is connected between the laser generator and the interface for external-power connection to protect the laser generator from damage caused by the current-overload of the laser generator.
    Type: Application
    Filed: September 29, 2003
    Publication date: December 2, 2004
    Inventor: Tzu-Yun Yeh
  • Publication number: 20040059902
    Abstract: A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the memory space and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.
    Type: Application
    Filed: July 29, 2003
    Publication date: March 25, 2004
    Inventors: Bi-Yun Yeh, Shu-Tzu Wang, Heng-Chen Ho
  • Patent number: 6691224
    Abstract: A method and computer system for accessing initialization data stored in a boot ROM's memory space which is not used by a BIOS contained in the boot ROM. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the boot ROM and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: February 10, 2004
    Assignee: Via Technologies, Inc.
    Inventors: Bi-Yun Yeh, Shu-Tzu Wang, Heng-Chen Ho
  • Publication number: 20030041223
    Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.
    Type: Application
    Filed: June 14, 2002
    Publication date: February 27, 2003
    Inventors: Bi-Yun Yeh, Jiin Lai, Sheng-Chung Wu