Patents by Inventor Yun-Biao Xin
Yun-Biao Xin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8741009Abstract: The inventive chemical-mechanical polishing system comprises a polishing component, a liquid carrier, and a polyether amine. The inventive method comprises chemically-mechanically polishing a substrate with the aforementioned polishing system.Type: GrantFiled: July 29, 2009Date of Patent: June 3, 2014Assignee: Cabot Microelectronics CorporationInventors: Jeffrey M. Dysard, Paul M. Feeney, Sriram P. Anjur, Timothy P. Johns, Yun-Biao Xin, Li Wang
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Publication number: 20100014074Abstract: A method of detecting one or more scratches on a surface of a wafer made of a non-semiconductor material is provided. A UV beam is produced from a UV illumination source. The UV beam is incident on a front surface of the wafer. The UV beam being characterized that for scratches of a given material having a UV cutoff wavelength ?cutoff, over 90% of the spectral system response SSR is at wavelengths below ?cutoff?5 nm and expressed as: ? 0 ? cutoff - 5 ? ? nm ? S ? ? S ? ? R ? ( ? ) > 0.90 · ? 0 ? ? S ? ? S ? ? R ? ( ? ) A reflected beam of scattering of the UV beam is detected in response to scratches on a surface of the wafer. The scattering is captured.Type: ApplicationFiled: July 16, 2008Publication date: January 21, 2010Inventors: Yun-Biao Xin, Martin Andrew Smith, Ronald Charles Dwelle, Gerard Vurens
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Patent number: 7649624Abstract: A method of detecting one or more scratches on a surface of a wafer made of a non-semiconductor material is provided. A UV beam is produced from a UV illumination source. The UV beam is incident on a front surface of the wafer. The UV beam being characterized that for scratches of a given material having a UV cutoff wavelength ?cutoff, over 90% of the spectral system response SSR is at wavelengths below ?cutoff?5 nm and expressed as: ? 0 ? cutoff - 5 ? nm ? SSR ? ( ? ) > 0.90 · ? 0 ? ? SSR ? ( ? ) A reflected beam of scattering of the UV beam is detected in response to scratches on a surface of the wafer. The scattering is captured.Type: GrantFiled: July 16, 2008Date of Patent: January 19, 2010Assignee: Crystal Technology, Inc.Inventors: Yun-Biao Xin, Martin Andrew Smith, Ronald Charles Dwelle, Gerard Vurens
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Publication number: 20090289033Abstract: The inventive chemical-mechanical polishing system comprises a polishing component, a liquid carrier, and a polyether amine. The inventive method comprises chemically-mechanically polishing a substrate with the aforementioned polishing system.Type: ApplicationFiled: July 29, 2009Publication date: November 26, 2009Inventors: Jeffrey M. Dysard, Paul M. Feeney, Sriram P. Anjur, Timothy P. Johns, Yun-Biao Xin, Li Wang
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Patent number: 7585340Abstract: The inventive chemical-mechanical polishing system comprises a polishing component, a liquid carrier, and a polyether amine. The inventive method comprises chemically-mechanically polishing a substrate with the aforementioned polishing system.Type: GrantFiled: April 27, 2006Date of Patent: September 8, 2009Assignee: Cabot Microelectronics CorporationInventors: Jeffrey M. Dysard, Paul M. Feeney, Sriram P. Anjur, Timothy P. Johns, Yun-Biao Xin, Li Wang
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Publication number: 20070251155Abstract: The inventive chemical-mechanical polishing system comprises a polishing component, a liquid carrier, and a polyether amine. The inventive method comprises chemically-mechanically polishing a substrate with the aforementioned polishing system.Type: ApplicationFiled: April 27, 2006Publication date: November 1, 2007Applicant: Cabot Microelectronics CorporationInventors: Jeffrey Dysard, Paul Feeney, Sriram Anjur, Timothy Johns, Yun-Biao Xin, Li Wang
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Patent number: 6709981Abstract: A method of manufacturing a semiconductor wafer includes providing an ingot of semiconductor material, slicing the wafer from the ingot, and processing the wafer to increase parallelism of the front surface and the back surface. A final polishing operation on at least the front surface is performed by positioning the wafer between a first pad and a second pad and obtaining motion of the front and back surfaces of the wafer relative to the first and second pads to maintain parallelism of the front and back surfaces and to produce a finish on at least the front surface of the wafer so that the front surface is prepared for integrated circuit fabrication. In another aspect, the wafer is rinsed by a rinsing fluid to increase hydrodynamic lubrication. Other methods are directed to conditioning the polishing pad and to handling wafers after polishing. An apparatus for polishing wafers is also included.Type: GrantFiled: August 13, 2001Date of Patent: March 23, 2004Assignee: MEMC Electronic Materials, Inc.Inventors: Alexis Grabbe, Mick Bjelopavlic, Ashley S. Hull, Michele L. Haler, Guoqiang (David) Zhang, Henry F. Erk, Yun-Biao Xin
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Publication number: 20030170920Abstract: A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.Type: ApplicationFiled: March 7, 2002Publication date: September 11, 2003Applicant: MEMC Electronic Materials, Inc.Inventors: Milind S. Bhagavat, Yun-Biao Xin, Gary L. Anderson, Brent F. Teasley
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Patent number: 6613591Abstract: A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.Type: GrantFiled: March 7, 2002Date of Patent: September 2, 2003Assignee: MEMC Electronic Materials, Inc.Inventors: Milind S. Bhagavat, Yun-Biao Xin, Gary L. Anderson, Brent F. Teasley
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Patent number: 6479386Abstract: A process for forming a semiconductor wafer which is single side polished improves nanotopology and flatness of the polished wafer. The process reduces the effect of back side surface features, such as edge ring phenomena and back side laser marks, on nanotopology, thereby improving oxide layer uniformity for chemical/mechanical planarization (CMP) processing, and flatness on the polished front side of the wafer after polishing. The wafer is mounted on a polishing block by wax. The edge ring causes certain deformation and stress in the wafer upon mounting, which is held by the wax. After mounting, the wax is heated to allow the wafer to relax, removing the stress, without degrading the bond of the wafer to the polishing block. The wafer is polished and removed from the polishing blocks. The polished surface substantially retains its shape after being de-mounted from the block.Type: GrantFiled: February 16, 2000Date of Patent: November 12, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Kan-Yin Ng, Yun-Biao Xin, Henry Erk, Darrel Harris, James Jose, Stephen Hensiek, Gene Hollander, Dennis Buese, Giovanni Negri
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Patent number: 6454635Abstract: A method for repairing a wafer carrier after plural processing operations during which the carrier holds a plurality of semiconductor wafers in a processing apparatus which removes wafer material by at least one of abrading and chemical reaction. The wafer carrier has holes for receiving respective ones of the wafers and removable annular inserts for each hole. Each insert is receivable in a respective one of the holes for engaging a peripheral edge of one of the wafers. The thickness of the insert is reduced during the successive processing operations. The method includes removing at least one of the inserts from the wafer carrier and installing at least one new insert in the wafer carrier having a thickness substantially greater than a minimum thickness to extend the useful life of the wafer carrier and to improve the flatness and parallelism of surfaces of wafers processed using the wafer carrier.Type: GrantFiled: August 8, 2000Date of Patent: September 24, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Guoqiang David Zhang, Yun-Biao Xin, Henry F. Erk
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Publication number: 20020052064Abstract: A method of manufacturing a semiconductor wafer includes providing an ingot of semiconductor material, slicing the wafer from the ingot, and processing the wafer to increase parallelism of the front surface and the back surface. A final polishing operation on at least the front surface is performed by positioning the wafer between a first pad and a second pad and obtaining motion of the front and back surfaces of the wafer relative to the first and second pads to maintain parallelism of the front and back surfaces and to produce a finish on at least the front surface of the wafer so that the front surface is prepared for integrated circuit fabrication. In another aspect, the wafer is rinsed by a rinsing fluid to increase hydrodynamic lubrication. Other methods are directed to conditioning the polishing pad and to handling wafers after polishing. An apparatus for polishing wafers is also included.Type: ApplicationFiled: August 13, 2001Publication date: May 2, 2002Inventors: Alexis Grabbe, Mick Bjelopavlic, Ashley S. Hull, Michele L. Haler, Guoqiang (David) Zhang, Henry F. Erk, Yun-Biao Xin
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Patent number: 6227944Abstract: A method for processing a semiconductor wafer sliced from a single-crystal ingot comprises subjecting the front and back surfaces of the wafer to a lapping operation to reduce the thickness of the wafer and to remove damage caused during slicing of the wafer. The wafer is then subjected to an etching operation to further reduce the thickness of the wafer and to further remove damage remaining after the lapping operation. The wafer is subsequently subjected to a double-side polishing operation to uniformly remove damage from the front and back surfaces caused by the lapping and etching operations, thereby improving the flatness of the wafer and leaving polished front and back surfaces. Finally, the back surface of the wafer is subjected to a back surface damaging operation in which damage is induced in the back surface of the wafer while the front surface is substantially protected against being damaged or roughened.Type: GrantFiled: March 25, 1999Date of Patent: May 8, 2001Assignee: MEMC Electronics Materials, Inc.Inventors: Yun-Biao Xin, Ichiro Yoshimura, Henry F. Erk, Ralph V. Vogelgesang, Stephen Wayne Hensiek
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Patent number: 6214704Abstract: A method of processing a semiconductor wafer sliced from a single-crystal ingot includes lapping front and back surfaces of the wafer to reduce the thickness of the wafer and to improve the flatness of the wafer. The front surface is subjected to fine grinding to reduce the damage on the front surface while leaving damage on the back surface intact. The front and back surfaces are simultaneously polished to improve the flatness of the wafer and to reduce wafer damage on the front and back surfaces. The wafer damage remaining on the back surface is greater than the wafer damage on the front surface. The wafer damage remaining on the back surface facilitates gettering.Type: GrantFiled: September 23, 1999Date of Patent: April 10, 2001Assignee: MEMC Electronic Materials, Inc.Inventor: Yun-Biao Xin
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Patent number: 6200908Abstract: A process for reducing the waviness of a semiconductor wafer utilizing plasma assisted chemical etching is disclosed. The process includes measuring the surface profile at discrete points on one surface of the wafer independent from the apposing surface, computing a dwell time versus position map based on the measured surface profiles, and selectively removing material from each surface of the wafer by plasma assisted chemical etching to reduce the waviness of the wafer.Type: GrantFiled: August 4, 1999Date of Patent: March 13, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Roland Vandamme, Ankur Desai, Dale Witte, Yun-Biao Xin
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Patent number: 6114245Abstract: A method of processing a semiconductor wafer comprises rough grinding the front and back surfaces of the wafer to quickly reduce the thickness of the wafer. The front and back surfaces are then lapped with a lapping slurry to further reduce the thickness of the wafer and reduce damage caused by the rough grinding. Lapping time is reduced by provision of the rough grinding step. The wafer is etched in a chemical etchant to further reduce the thickness of the wafer and the front surface of the wafer is polished using a polishing slurry to reduce the thickness of the wafer down to a predetermined final wafer thickness. A fine grinding step may be added to eliminate lapping and/or reduce polishing time.Type: GrantFiled: July 19, 1999Date of Patent: September 5, 2000Assignee: MEMC Electronic Materials, Inc.Inventors: Roland Vandamme, Yun-Biao Xin, Zhijian Pei