Abstract: Provided is an ultra large-width coating device applied to a consecutive process. More particularly, the present invention relates to a coating device capable of maximizing productivity by consecutively manufacturing a large-width film without reducing physical properties of the manufactured film by overcoming a problem in that a coating width is limited during a coating process using the existing contact type coating roller, and a method for manufacturing an ultra large-width membrane using the same.

Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A method of forming a non-volatile memory device includes the following steps. First and second cell gates are formed in a cell region. First and second peripheral gates are formed in a peripheral-region. A first insulating layer is formed over the first and second cell gates and the first and second peripheral gates. A second conductive layer is formed over the first insulating layer. A third insulating layer is formed over the second conductive layer. Selected portions of the third insulating layer, the second conductive layer, and the first insulating layer are removed to form an inter-gate plug provided between the first and second cell gates. The inter-gate plug completely fills a space defined between the first and second cell gates.

Abstract: A method of forming a non-volatile memory device includes the following steps. First and second cell gates are formed in a cell region. First and second peripheral gates are formed in a peripheral-region. A first insulating layer is formed over the first and second cell gates and the first and second peripheral gates. A second conductive layer is formed over the first insulating layer. A third insulating layer is formed over the second conductive layer. Selected portions of the third insulating layer, the second conductive layer, and the first insulating layer are removed to form an inter-gate plug provided between the first and second cell gates. The inter-gate plug completely fills a space defined between the first and second cell gates.

Abstract: A non-volatile memory device includes first and second cell gates formed in a cell region; first and second peripheral gates are formed in a peri-region; and an inter-gate plug is provided between the first and second cell gates. The inter-gate plug includes a first insulating layer, a second conductive layer formed over the first insulating layer, and a third insulating layer formed over the second conductive layer.

Abstract: A page buffer circuit of a flash memory device has small consumption power. The page buffer circuit utilizes different voltages are supplied to the latch circuits in the standby and normal modes to reduce consumption power in the standby mode.