Patents by Inventor Yun Che

Yun Che has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230342108
    Abstract: An example method includes receiving, by one or more processors of a computing device, audio data recorded by one or more microphones of the computing device; and generating, based on the audio data and by the one or more processors, one or more structured sound records, a first structured sound record of the one or more structured sound records including: a description of a first sound, the description including a descriptive label of the first sound, the descriptive label different than a text transcription of the first sound, and a time stamp indicating a time at which the first sound occurred; and outputting a graphical user interface including timeline representation of the one or more structured sound records.
    Type: Application
    Filed: August 31, 2021
    Publication date: October 26, 2023
    Inventors: Dimitri Kanevsky, Sagar Savla, Ausmus Chang, Chiawei Liu, Daniel P W Ellis, Jinho Kim, Justin Stuart Paul, Sharlene Yuan, Alex Huang, Yun Che Chung, Chelsey Fleming
  • Patent number: 8857111
    Abstract: A composite damper includes a first connector, a second connector and at least a dampening device. The first connector and the second connector are relative movable to each other, and the at least one dampening device is received between the first connector and the second connector. The dampening device comprises at least a rigid member and at least a dampening member, wherein the rigid member has the properties of high stiffness and low damping, while the dampening member has the properties of low stiffness and high damping. With such design, the composite damper could absorb vibrations during earthquakes.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 14, 2014
    Assignees: National Cheng Kung University, Tongji University
    Inventors: Yun-Che Wang, Bin Zhao, Hai-Jie Ge, Chih-Chin Ko
  • Patent number: 8728256
    Abstract: A heat-resistant aluminum alloy material with high strength and preparation method thereof are provided. The aluminum alloy material comprises (by weight %): Cu: 1.0˜10.0, Mn: 0.05˜1.5, Cd: 0.01˜0.5, Ti: 0.01˜0.5%, B: 0.01˜0.2 or C: 0.0001˜0.15, Zr: 0.01˜1.0, R: 0.001˜3 or (R1+R2): 0.001˜3, RE: 0.05˜5, and balance Al:, wherein, R, R1, and R2 include Be, Co, Cr, Li, Mo, Nb, Ni, W. The Al alloy has the advantages of narrow quasi-solid phases temperature range of alloys, low hot cracking liability during casting improved high temperature strength and high heat resistance.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 20, 2014
    Assignee: Guizhou Hua-Ke Aluminum-Materials Engineering Research Co., Ltd.
    Inventors: Yun Che, Zhongke Zhang, Sanquan Men, Xinmeng Chen, Guangyou Xu, Xiang Li
  • Publication number: 20140000185
    Abstract: A composite damper includes a first connector, a second connector and at least a dampening device. The first connector and the second connector are relative movable to each other, and the at least one dampening device is received between the first connector and the second connector. The dampening device comprises at least a rigid member and at least a dampening member, wherein the rigid member has the properties of high stiffness and low damping, while the dampening member has the properties of low stiffness and high damping. With such design, the composite damper could absorb vibrations during earthquakes.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 2, 2014
    Inventors: YUN-CHE WANG, BIN ZHAO, HAI-JIE GE, CHIH-CHIN KO
  • Publication number: 20120247453
    Abstract: A dehydration device includes a solar energy collection device connected with a water source so as to transfer solar energy into thermo energy which heats water that is supplied from the water source. A water storage device includes at least one hot water tank which has a heater connected to the solar energy collection device. The water heated by the solar energy collection device is stored in the at least one hot water tank. A heat-exchange device has a pipe connected with the water storage device, and an air delivery unit which blows air toward the pipe to form hot air to dehydrate foods. A windmill generates electric power which is provided to the dehydration device. The dehydration device uses green energy to dehydrate foods to keep proper freshness and nutrition. The dehydration device is easily moved and friendly to the environment.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 4, 2012
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventor: YUN-CHE WEN
  • Publication number: 20120152414
    Abstract: A heat-resistant aluminum alloy material with high strength and preparation method thereof are provided. The aluminum alloy material comprises (by weight %): Cu: 1.0˜10.0, Mn: 0.05˜1.5, Cd: 0.01˜0.5, Ti: 0.01˜0.5%, B: 0.01˜0.2 or C: 0.0001˜0.15, Zr: 0.01˜1.0, R: 0.001˜3 or (R1+R2): 0.001˜3, RE: 0.05˜5, and balance Al:, wherein, R, R1, and R2 include Be, Co, Cr, Li, Mo, Nb, Ni, W. The Al alloy has the advantages of narrow quasi-solid phases temperature range of alloys, low hot cracking liability during casting improved high temperature strength and high heat resistance.
    Type: Application
    Filed: August 4, 2010
    Publication date: June 21, 2012
    Inventors: Yun Che, Zhongke Zhang, Sanquan Men, Xinmeng Chen, Guangyou Xu, Xiang Li
  • Publication number: 20110176957
    Abstract: A high strength casting aluminum alloy material comprises (in weight %) Cu 2.0-6.0%, Mn 0.05-1.0%, Ti 0.01-0.5%, Cr 0.01-0.2%, Cd 0.01-0.4%, Zr 0.01-0.25%, B 0.005-0.04%, rare earth 0.05-0.3%, and balance aluminum and trace impurities. The alloy has reduced cost.
    Type: Application
    Filed: July 2, 2009
    Publication date: July 21, 2011
    Inventors: Yun Che, Jinde Lu, Zhongke Zhang, De'en Zhang, Xiaoyan Zhang, Guangpu Yan
  • Publication number: 20100107934
    Abstract: An intensive pallet and a unit direction plank for the same are provided, and the pallet comprises a plurality of first direction planks spaced from each other and a plurality of second direction planks spaced from each other. The second direction plank and the first direction plank stack and cross. Two frame holes are formed in each unit of first direction plank. One frame hole communicates with a next spaced frame hole of the unit first direction plank. A plurality of first ribs are formed at the top side of each frame hole. The frame holes may be inserted by the insertion levers of a forklift. The first ribs are provided to enhance the top sides of frame holes into which the levers are inserted.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Inventor: Yun Che Hsieh
  • Patent number: 7154422
    Abstract: The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC's parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: December 26, 2006
    Assignee: National Cheng Kung University
    Inventor: Yun-Che Wen
  • Publication number: 20060001560
    Abstract: The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC's parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 5, 2006
    Inventor: Yun-Che Wen
  • Patent number: 6504849
    Abstract: A communication node is configured to automatically select an optimum common operational mode between itself and a link partner. The communication node sends advertisement packets across a fiber optic medium in order to broadcast its operational capabilities to the link partner. These operational capabilities may include 10BASE-FL and 100BASE-FL. Transitions may be inserted between the advertisement packets which may include clock pulses, data pulses and transitions. The communication node may be attached to a network having a bus architecture and may further be configured to identify an idle signal.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: January 7, 2003
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yun-Che Wang, Chuan-Ding Arthur Hsu, Venkataraman Sukavanam
  • Patent number: 6229811
    Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: May 8, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, M. Magdy Talaat, Yun-Che Wang, Michael J. Kasper
  • Patent number: 6055241
    Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: April 25, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, M. Magdy Talaat, Yun-Che Wang, Michael J. Kasper
  • Patent number: 5731719
    Abstract: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: March 24, 1998
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yun-Che Wang, Thomas Korn, Chuan-Ding Arthur Hsu
  • Patent number: 5663665
    Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: September 2, 1997
    Assignee: Cypress Semiconductor Corp.
    Inventors: Yun-Che Wang, Gaurang Shah
  • Patent number: 5387911
    Abstract: A method and apparatus for using a modified 8B/10B system for transmitting 10 bit wide data packets in 12 bit code in which 5B/6B encoder/decoders separate the 10 bit wide data into two 5 bit nibbles. Unique special codes are provided which are not capable of aliasing with other 12 bit code words to provide reliable byte boundaries.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: February 7, 1995
    Inventors: Marc C. Gleichert, Arthur Hsu, Yun-Che Wang
  • Patent number: 5347547
    Abstract: A method and apparatus for improving the reliability of resynchronization in a serial frame based protocol communication system which can avoid resynchronization when line loss erroneously causes data to appear as a redundant unique code pattern. The synchronization is only initiated if two such unique code pattern bytes are received within a specified time separation.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: September 13, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marc C. Gleichert, Yun-Che Wang
  • Patent number: 5304996
    Abstract: An 8B/10B encoder which provides an output of one of a pair of opposite disparity non-complementary 8B/10B command code outputs responsive to RD and selected command inputs.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: April 19, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arthur Hsu, Yun-Che Wang
  • Patent number: 4878028
    Abstract: Apparatus is disclosed for introducing a precompensation delay in the path of a data signal to be written onto a magnetic medium, such as a floppy or hard disk. The apparatus includes a current controlled oscillator made up of delay elements having current control nodes, and means for controlling the current level being drawn from the current control nodes. The latter means includes three matched voltage controlled current sources having their outputs connected through a current splitter to the current control nodes, and bypass transistors for decoupling two of the voltage controlled current sources in response to a delay selection signal indicating whether the subject data pulse should be precompensated early, nominal or late.
    Type: Grant
    Filed: February 12, 1987
    Date of Patent: October 31, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yun-Che Wang, Paul H. Scott