Abstract: A composite damper includes a first connector, a second connector and at least a dampening device. The first connector and the second connector are relative movable to each other, and the at least one dampening device is received between the first connector and the second connector. The dampening device comprises at least a rigid member and at least a dampening member, wherein the rigid member has the properties of high stiffness and low damping, while the dampening member has the properties of low stiffness and high damping. With such design, the composite damper could absorb vibrations during earthquakes.

Abstract: A composite damper includes a first connector, a second connector and at least a dampening device. The first connector and the second connector are relative movable to each other, and the at least one dampening device is received between the first connector and the second connector. The dampening device comprises at least a rigid member and at least a dampening member, wherein the rigid member has the properties of high stiffness and low damping, while the dampening member has the properties of low stiffness and high damping. With such design, the composite damper could absorb vibrations during earthquakes.

Abstract: A communication node is configured to automatically select an optimum common operational mode between itself and a link partner. The communication node sends advertisement packets across a fiber optic medium in order to broadcast its operational capabilities to the link partner. These operational capabilities may include 10BASE-FL and 100BASE-FL. Transitions may be inserted between the advertisement packets which may include clock pulses, data pulses and transitions. The communication node may be attached to a network having a bus architecture and may further be configured to identify an idle signal.

Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

Abstract: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.

Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

Abstract: A method and apparatus for using a modified 8B/10B system for transmitting 10 bit wide data packets in 12 bit code in which 5B/6B encoder/decoders separate the 10 bit wide data into two 5 bit nibbles. Unique special codes are provided which are not capable of aliasing with other 12 bit code words to provide reliable byte boundaries.

Abstract: A method and apparatus for improving the reliability of resynchronization in a serial frame based protocol communication system which can avoid resynchronization when line loss erroneously causes data to appear as a redundant unique code pattern. The synchronization is only initiated if two such unique code pattern bytes are received within a specified time separation.

Abstract: An 8B/10B encoder which provides an output of one of a pair of opposite disparity non-complementary 8B/10B command code outputs responsive to RD and selected command inputs.

Abstract: Apparatus is disclosed for introducing a precompensation delay in the path of a data signal to be written onto a magnetic medium, such as a floppy or hard disk. The apparatus includes a current controlled oscillator made up of delay elements having current control nodes, and means for controlling the current level being drawn from the current control nodes. The latter means includes three matched voltage controlled current sources having their outputs connected through a current splitter to the current control nodes, and bypass transistors for decoupling two of the voltage controlled current sources in response to a delay selection signal indicating whether the subject data pulse should be precompensated early, nominal or late.