Abstract: A dehydration device includes a solar energy collection device connected with a water source so as to transfer solar energy into thermo energy which heats water that is supplied from the water source. A water storage device includes at least one hot water tank which has a heater connected to the solar energy collection device. The water heated by the solar energy collection device is stored in the at least one hot water tank. A heat-exchange device has a pipe connected with the water storage device, and an air delivery unit which blows air toward the pipe to form hot air to dehydrate foods. A windmill generates electric power which is provided to the dehydration device. The dehydration device uses green energy to dehydrate foods to keep proper freshness and nutrition. The dehydration device is easily moved and friendly to the environment.

Abstract: The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC's parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.

Abstract: The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC's parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.