Patents by Inventor Yun-Chen Chou
Yun-Chen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11842769Abstract: At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.Type: GrantFiled: April 14, 2022Date of Patent: December 12, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Tien-Yen Wang, Yun-Chen Chou, Chun-Hsiung Hung
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Publication number: 20230335187Abstract: At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Tien-Yen Wang, Yun-Chen Chou, Chun-Hsiung Hung
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Publication number: 20230307014Abstract: A sensing module, a memory device, and a sensing method are provided to perform a read operation so that the un-programmed/programmed state of a memory cell is identified. The sensing module includes a sensing amplifier and a current sink, and both are electrically connected to the memory cell. The sensing amplifier generates a sensing current and identifies the un-programmed/programmed state of the memory cell accordingly. The current sink receives a reference current being equivalent to the summation of the sensing current and a cell current flowing through the memory cell. The reference current is constant, and the sensing current is changed with the cell current. The cell current is generated based on a high read voltage and a low read voltage applied to the memory cell. The sensing current is higher if the memory cell is un-programmed, and the sensing current is lower if the memory cell is programmed.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Inventors: Yun-Chen CHOU, Tien-Yen WANG, Chun-Hsiung HUNG
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Patent number: 11049557Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.Type: GrantFiled: July 19, 2019Date of Patent: June 29, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yun-Chen Chou, Yung-Feng Lin, Hsin-Yi Ho
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Publication number: 20210020235Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.Type: ApplicationFiled: July 19, 2019Publication date: January 21, 2021Applicant: Macronix International Co., Ltd.Inventors: Yun-Chen Chou, Yung-Feng Lin, Hsin-Yi Ho
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Patent number: 10297316Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.Type: GrantFiled: August 28, 2017Date of Patent: May 21, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yung-Feng Lin, Yun-Chen Chou, Hsin-Yi Ho
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Publication number: 20190066778Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Inventors: Yung-Feng Lin, Yun-Chen Chou, Hsin-Yi Ho
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Patent number: 8456906Abstract: An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.Type: GrantFiled: November 29, 2011Date of Patent: June 4, 2013Assignee: Macronix International Co., Ltd.Inventors: Hsin-Yi Ho, Chun-Hsiung Hung, Yun-Chen Chou
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Publication number: 20120069671Abstract: An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.Type: ApplicationFiled: November 29, 2011Publication date: March 22, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsin-Yi Ho, Chun-Hsiung Hung, Yun-Chen Chou
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Patent number: 8094494Abstract: In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.Type: GrantFiled: October 9, 2009Date of Patent: January 10, 2012Assignee: Macronix International Co., Ltd.Inventors: Hsin-Yi Ho, Chun-Hsiung Hung, Yun-Chen Chou
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Publication number: 20110085378Abstract: In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsin-Yi Ho, Chun-Hsiung Hung, Yun-Chen Chou