Patents by Inventor Yun-Chen Hsieh
Yun-Chen Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352442Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230274976Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.Type: ApplicationFiled: April 18, 2023Publication date: August 31, 2023Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11742317Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: October 17, 2019Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230207478Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Chen-Hua Yu, Hui-Jung Tsai
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Patent number: 11651994Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.Type: GrantFiled: March 29, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230115729Abstract: Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
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Patent number: 11600574Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.Type: GrantFiled: December 14, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
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Patent number: 11587902Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: September 19, 2019Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11527466Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.Type: GrantFiled: April 5, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
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Patent number: 11404308Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.Type: GrantFiled: November 16, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
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Publication number: 20210242083Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.Type: ApplicationFiled: March 29, 2021Publication date: August 5, 2021Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20210225751Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
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Patent number: 10971442Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.Type: GrantFiled: February 1, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
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Publication number: 20210098383Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
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Patent number: 10964591Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.Type: GrantFiled: June 24, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20210082745Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.Type: ApplicationFiled: November 16, 2020Publication date: March 18, 2021Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
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Patent number: 10892228Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.Type: GrantFiled: May 20, 2019Date of Patent: January 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
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Patent number: 10886231Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.Type: GrantFiled: October 11, 2018Date of Patent: January 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
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Patent number: 10867874Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.Type: GrantFiled: January 21, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kuo
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Patent number: 10840129Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.Type: GrantFiled: December 17, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai