Patents by Inventor Yun-Chi Liu

Yun-Chi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966711
    Abstract: Embodiments of the present disclosure relate to a solution for translation verification and correction. According to the solution, a neural network is trained to determine an association degree among a group of words in a source or target language. The neural network can be used for translation verification and correction. According to the solution, a group of words in a source language and translations of the group of words in a target language are obtained. An association degree among the group of words and an association degree among the translations can be determined by using the trained neural network. Then, whether there is a wrong translation can be determined based on the association degrees. In some embodiments, corresponding methods, systems and computer program products are provided.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Guang Ming Zhang, Xiaoyang Yang, Hong Wei Jia, Mo Chi Liu, Yun Wang
  • Publication number: 20240119350
    Abstract: According to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new AI model. A runtime matrix that includes identifiers of runtime environments is accessed. The matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained AI models using each of the plurality of types of processing. One or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. Identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: He Sheng Yang, Mo Chi Liu, Yun Wang, Hong Wei Jia, Wu Yan, Xiaoyang Yang
  • Publication number: 20240096941
    Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 21, 2024
    Inventors: SHIH-JUNG TU, PO-WEI LIU, TSUNG-YU YANG, YUN-CHI WU, CHIEN HUNG LIU
  • Publication number: 20240097027
    Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming PAN, Chia-Ta HSIEH, Po-Wei LIU, Yun-Chi WU
  • Publication number: 20170337028
    Abstract: A method for modular display frame is provided. The method includes the following steps. A number of display devices are combined to form a composite screen. A directional code including a number of positioning marks is displayed on each display device. The directional code displayed on each display device is scanned. Orientation information of each display device is obtained. A unique pattern is displayed on each display device. The composite screen is captured to generate a first image. Spatial location information of each display device is obtained from the first image. A number of display parameters corresponding to the display devices are calculated according to the orientation information and the spatial location information of the display devices. The display parameters are transmitted to the display devices. Each display device displays a regional frame according to the display parameters of the corresponding display device.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 23, 2017
    Applicant: Qisda Corporation
    Inventors: Yu-Fu Fan, Ming-Zong Chen, Yun-Chi Liu