Abstract: According to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new AI model. A runtime matrix that includes identifiers of runtime environments is accessed. The matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained AI models using each of the plurality of types of processing. One or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. Identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process.

Abstract: To make an alternating current (AC) stress test easier to perform in a wafer, an AC stress test circuit for performing the AC stress test on a test device fabricated in a test region of the wafer includes an oscillator module fabricated in the test region, a diode module fabricated in the test region coupled to an output of the oscillator module, and a select transistor fabricated in the test region having a gate terminal coupled to an output of the diode module, a second terminal coupled to a gate of the test device, and a third terminal coupled to a test voltage source.

Abstract: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.

Abstract: A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.

Abstract: This invention provides a method for forming a microcrystalline polysilicon layer by using silane or dislane with introducing hydrogen gas. This microcrystalline polysilicon layer can be used as a floating gate of a flash memory to improve the character of the flash memory.

Abstract: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.

Abstract: The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer of the semiconductor wafer, the first insulating layer including a first index of refraction, forming a second insulating layer over the first insulating layer, the second insulating layer including a second index of refraction smaller than the first index of refraction, removing the second insulating layer by a planarizing process, and detecting a change in index of refraction during the planarizing process.

Abstract: A method for fabricating a silicon oxide/silicon nitride/silicon oxide stacked layer structure is described. A bottom oxide layer is formed over a substrate. A surface treatment is then performed on the first silicon oxide layer to form an interface layer over the bottom oxide layer. The surface treatment is conducted in a nitrogen ambient. Thereafter, a silicon nitride layer is formed over the interface layer, followed by forming an upper silicon oxide layer over the silicon nitride layer.

Abstract: The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

Abstract: To improve the edge breakdown caused by edge electrical field at the tunnel oxide of high-density flash memory, a bird's beak is formed at the edge of the active region of the flash memory to prevent the corner of the tunnel oxide layer formed later on the active region from being excessively sharp, which will result in localized intense electrical field, and further lead to breakdown caused by the edge electrical field.

Abstract: This invention relates to a method for making the gate dielectric layer, more particularly, to the method for making the interface between the gate dielectric layer and silicon substrate by using oxygen radicals and hydroxyl radicals. In the method, we send the wafers, which has passed through the cleaning process for the silicon substrate, to the chamber at first and then transmit the first reaction gas, which comprises the nitric monoxide and the oxygen or comprises the nitric monoxide and nitrogen, to the chamber to form a silicon nitride layer or a silicon oxynitride layer on the first surface of the silicon substrate to be a gate. Next, we transmit the second reaction gas, which comprises the oxygen and the hydrogen, to the chamber and make the second reaction gas to be dissociated into the oxygen radicals and the hydroxyl radicals.