Abstract: A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

Abstract: A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

Abstract: A power converter, a synchronous power converter system and a method of determining switching frequency are provided. A processor is configured to output a synchronous clock signal corresponding to a first switching frequency. A plurality of first-stage power converters are coupled to the processor, and configured to generate a plurality of first output voltages corresponding to the first switching frequency according to the synchronous clock signal and a system voltage. At least one second-stage power converter is coupled to the processor and one of the plurality of first-stage power converters, and configured to generate a second output voltage corresponding to a second switching frequency according to the synchronous clock signal, a multiplied frequency control signal and one of the plurality of first output voltages. The second switching frequency is a multiple of the first switching frequency.

Abstract: A power converter, a synchronous power converter system and a method of determining switching frequency are provided. A processor is configured to output a synchronous clock signal corresponding to a first switching frequency. A plurality of first-stage power converters are coupled to the processor, and configured to generate a plurality of first output voltages corresponding to the first switching frequency according to the synchronous clock signal and a system voltage. At least one second-stage power converter is coupled to the processor and one of the plurality of first-stage power converters, and configured to generate a second output voltage corresponding to a second switching frequency according to the synchronous clock signal, a multiplied frequency control signal and one of the plurality of first output voltages. The second switching frequency is a multiple of the first switching frequency.

Abstract: A synchronous power converter system is provided. The system includes a processor circuit and a plurality of power converters. The processor circuit outputs a plurality of clock signals having the same frequency. The power converters respectively receive the clock signals. Each of the power converters includes an oscillator circuit, a frequency detector circuit, a compensator circuit, a controller circuit, and a switch circuit. The oscillator circuit outputs an oscillation signal. The frequency detector circuit receives the clock signal and the oscillation signal and detects a clock frequency of the clock signal and an oscillation frequency of the oscillation signal to output a frequency detected signal. The compensator circuit outputs a compensating signal according to the frequency detected signal. The controller circuit controls the switch circuit according to the compensating signal.

Abstract: A synchronous power converter system is provided. The system includes a processor circuit and a plurality of power converters. The processor circuit outputs a plurality of clock signals having the same frequency. The power converters respectively receive the clock signals. Each of the power converters includes an oscillator circuit, a frequency detector circuit, a compensator circuit, a controller circuit, and a switch circuit. The oscillator circuit outputs an oscillation signal. The frequency detector circuit receives the clock signal and the oscillation signal and detects a clock frequency of the clock signal and an oscillation frequency of the oscillation signal to output a frequency detected signal. The compensator circuit outputs a compensating signal according to the frequency detected signal. The controller circuit controls the switch circuit according to the compensating signal.

Abstract: A power converter having fast transient response is provided. The power converter includes a voltage detector circuit and a compensator circuit. The voltage detector circuit includes a plurality of resistors, a plurality of comparators, and a detection control circuit. The resistors are connected in series with each other and grounded. First and second terminals of one of the resistors are respectively connected to a reference voltage and a first terminal of the adjacent resistor. First and second terminals of another of the resistors are respectively connected to a second terminal of the adjacent resistor and grounded. First input terminals of the comparators are respectively connected to second terminals of the resistors. The detection control circuit outputs control signals according to comparison signals. The compensator circuit outputs a compensating signal according to the control signals. A main control circuit controls switch circuits according to the compensating signal.

Abstract: A multi-channel power system and a method of controlling a phase shift of the same are provided. The multi-channel power system includes one or more first DC to DC converters and one or more second DC to DC converters. The first DC-DC converter outputs a first pulse width modulated signal having a first default frequency. When the first DC-DC converter receives a reference clock signal, it outputs the first pulse width modulated signal having a frequency that is the same as that of the reference clock signal. The first DC-DC converter outputs a phase-shifted clock signal having a preset phase shift relative to the first pulse width modulated signal. The second DC-DC converter outputs a second pulse width modulated signal having a second default frequency. The second DC-DC converter outputs the second pulse width modulated signal having the preset phase shift according to the phase shift clock signal.

Abstract: A power converting device and a method thereof are provided. The power converting device includes a filter circuit, a zero-crossing comparison circuit, a counting circuit, a logic circuit, an oscillation circuit, and a control circuit. The zero-crossing comparison circuit outputs a zero-crossing signal when an inductor current is equal to a zero current. The counting circuit counts a time interval between two consecutive time points at which the inductor currents are equal to the zero current in a low power mode. When the logic circuit determines that the time interval is greater than a first time threshold, the control circuit transmits a first oscillating signal to the filter circuit from the oscillation circuit; otherwise, it outputs a second oscillating signal; it outputs a pulse-skipping mode signal when the interval time is less than a second time threshold.

Abstract: A phase adjusting device provided includes a main delay circuit, a first converter, a second converter, a first buck circuit, and a second buck circuit. The main delay circuit receives an input clock signal to generate a main delay signal. The first converter receives the input clock signal to generate a first conversion signal. The second converter is coupled to the main delay circuit to receive the main delay signal and generate a second conversion signal. The first buck circuit is coupled to the first converter to receive the first conversion signal and generate a first buck voltage. The second buck circuit is coupled to the second converter to receive the second conversion signal and generate a second buck voltage. A first phase difference is formed between the main delay signal and the input clock signal.