Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: A decoding method adopting an algorithm with weight-based adjusted parameters and a decoding system are provided. The decoding method is applied to a decoder. M×N low density parity check codes (LDPC codes) having N variable nodes and M check nodes are generated from input signals. In the decoding method, information of the variable nodes and the check nodes is initialized. The information passed from the variable nodes to the check nodes is formed after multiple iterations. After excluding a connection to be calculated, a product of the remaining connections between the variable nodes and the check nodes is calculated. Next, an estimated first minimum or an estimated second minimum can be calculated with multi-dimensional parameters. The information passed from the check nodes to the variable nodes can be updated for making a decision.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: A detection circuit, including a first connecting terminal, an SPI bus, and a security component, is provided. The first connecting terminal is configured to be detachably connected to the main board. The security component is coupled to the first connecting terminal and the SPI bus. The security component forms a first loop with the main board, and is configured to detect a loop state of the first loop. The security component locks the SPI bus when the first loop is being detected by the security component to be disconnected.

Abstract: An electronic device includes a substrate, a first conductive pad and a chip. The first conductive pad is disposed on the substrate. The chip includes a second conductive pad electrically connected to the first conductive pad, and the first conductive pad is disposed between the substrate and the second conductive pad. The first conductive pad has a first groove.

Abstract: A detection circuit, including a first connecting terminal, an SPI bus, and a security component, is provided. The first connecting terminal is configured to be detachably connected to the main board. The security component is coupled to the first connecting terminal and the SPI bus. The security component forms a first loop with the main board, and is configured to detect a loop state of the first loop. The security component locks the SPI bus when the first loop is being detected by the security component to be disconnected.

Abstract: A signal processing method in a digital-domain includes: adding a random number sequence signal into a time-domain input signal to generate a time-domain processed input signal; performing a Fourier transform operation upon the time-domain processed input signal to generate a frequency-domain processed input signal; performing an equalizer operation upon the frequency-domain processed input signal to generate a frequency-domain output signal according to coefficients of the equalizer operation; performing an inverse Fourier transform operation upon the frequency-domain output signal to generate a time-domain output signal; generating a decision output signal and generating a time-domain error signal according to the time-domain output signal; and determining the coefficients according to the time-domain error signal and the frequency-domain processed input signal.

Abstract: A signal processing method in a digital-domain includes: adding a random number sequence signal into a time-domain input signal to generate a time-domain processed input signal; performing a Fourier transform operation upon the time-domain processed input signal to generate a frequency-domain processed input signal; performing an equalizer operation upon the frequency-domain processed input signal to generate a frequency-domain output signal according to coefficients of the equalizer operation; performing an inverse Fourier transform operation upon the frequency-domain output signal to generate a time-domain output signal; generating a decision output signal and generating a time-domain error signal according to the time-domain output signal; and determining the coefficients according to the time-domain error signal and the frequency-domain processed input signal.

Abstract: An electronic device includes a substrate, a first conductive pad and a chip. The first conductive pad is disposed on the substrate. The chip includes a second conductive pad electrically connected to the first conductive pad, and the first conductive pad is disposed between the substrate and the second conductive pad. The first conductive pad has a first groove.