Patents by Inventor Yun-Ching HUNG

Yun-Ching HUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTERCONNECTION STRUCTURE AND PACKAGE STRUCTURE
    Publication number: 20240297086
    Abstract: An interconnection structure and a package structure are provided. The interconnection structure includes a substrate, a conductive layer, a bonding layer, and a moderating layer. The conductive layer is over the substrate and has a top surface. The bonding layer is over the top surface of the conductive layer. The moderating layer is between the conductive layer and the bonding layer and configured to mitigate an increase in a surface roughness of the top surface of the conductive layer during an electroless plating process for forming the bonding layer.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 5, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Wei CHIANG, Yun-Ching HUNG, Yung-Sheng LIN
  • Semiconductor packages
    Patent number: 11798907
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Sheng Lin, Yun-Ching Hung, An-Hsuan Hsu, Chung-Hung Lai
  • Semiconductor package and method for manufacturing the same
    Patent number: 11430761
    Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yun-Ching Hung, Yung-Sheng Lin, Chin-Li Kao
  • SEMICONDUCTOR PACKAGES
    Publication number: 20220148989
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Sheng LIN, Yun-Ching HUNG, An-Hsuan HSU, Chung-Hung LAI
  • SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210257331
    Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yun-Ching HUNG, Yung-Sheng LIN, Chin-Li KAO