Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.

Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.

Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.

Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.

Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.

Abstract: Embodiments of the disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first metal wiring layer disposed on the semiconductor substrate, an interlayer dielectric layer (ILD) disposed on the first metal wiring layer, a second metal wiring layer disposed on the interlayer dielectric layer, and a first via and a second via disposed in the interlayer dielectric layer. The second via is on the first via, and there is not any metal wiring layer in the interlayer dielectric layer.

Abstract: Embodiments of the disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first metal wiring layer disposed on the semiconductor substrate, an interlayer dielectric layer (ILD) disposed on the first metal wiring layer, a second metal wiring layer disposed on the interlayer dielectric layer, and a first via and a second via disposed in the interlayer dielectric layer. The second via is on the first via, and there is not any metal wiring layer in the interlayer dielectric layer.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.

Abstract: A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure.

Abstract: A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure.

Abstract: A high voltage (HV) semiconductor device includes: a semiconductor substrate having a first conductivity type; a gate structure disposed over a portion of the semiconductor substrate; a pair of spacers respectively disposed over a sidewall of the gate structure, wherein one of the spacers is a composite spacer comprising a first insulating spacer contacting the gate structure, a dummy gate structure, and a second insulating spacer; a first drift region disposed in a portion of the semiconductor, underlying a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite to the first conductivity type; and a pair of doping regions, respectively disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, wherein the pair of doping regions include the second conductivity type and one of the doping regions is disposed in the first drift region.