Abstract: A method (480, 580) of depositing layers of a thin-film transistor on a substrate using a sputter deposition source comprising at least one first pair of electrodes and at least one second pair of electrodes, the method comprising moving (482, 582) the substrate to a first vacuum chamber; depositing (484, 584) a first layer of the layers on the substrate by supplying the at least one first pair of electrodes with bipolar pulsed DC voltage, wherein a first material of the first layer comprises a first metal oxide; moving (486, 586) the substrate from the first vacuum chamber to a second vacuum chamber without a vacuum break; and depositing (488, 588) a second layer of the layers on the first layer by supplying the at least one second pair of electrodes with bipolar pulsed DC voltage, wherein a second material of the second layer comprises a second metal oxide, the second material being different from the first material.

Abstract: A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150° C. to about 275° C.

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract: A thin film transistor comprises a transparent substrate, a gate is disposed on the transparent substrate, a gate insulator is disposed on the gate and the transparent substrate, an active layer is disposed on the gate insulator, an electrode layer is electrically connected the active layer and the portion of the active layer is exposed, and an ultraviolet light absorbing layer is disposed on the electrode layer. By using the advantage of the ultraviolet light absorbing layer with the range of visible light transmittance and with the component protection, preventing the optical characteristics of the thin film transistor from the outside moisture is achieved, and by adjusting the parameters in the thin film deposition process to change its conductivity.

Abstract: A thin film transistor comprises a transparent substrate, a gate is disposed on the transparent substrate, a gate insulator is disposed on the gate and the transparent substrate, an active layer is disposed on the gate insulator, an electrode layer is electrically connected the active layer and the portion of the active layer is exposed, and an ultraviolet light absorbing layer is disposed on the electrode layer. By using the advantage of the ultraviolet light absorbing layer with the range of visible light transmittance and with the component protection, preventing the optical characteristics of the thin film transistor from the outside moisture is achieved, and by adjusting the parameters in the thin film deposition process to change its conductivity.