Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate and a vertical transistor. The vertical transistor is disposed on the substrate. The vertical transistor comprises an insulating layer, a source, a drain, a gate insulating layer and a gate. The source and the drain are arranged below and above the insulating layer, and the gate insulating layer surrounds the insulating layer, the source and the drain. The gate covers the gate insulating layer, and the gate insulating layer separates the gate from the source and separates the gate from the drain.

Abstract: A memory circuit includes a first memory cell array configured to store data, and a second memory cell array. The second memory cell array is configured as a first logic circuit or a second logic circuit in response to a first set of control signals. The first logic circuit is configured to perform a first logic function on a first set of data signals based on a second set of control signals. The second logic circuit is configured to perform a second logic function on the first set of data signals based on the second set of control signals. The second logic function is different from the first logic function. The first set of data signals is part of the data stored in the first memory cell array. The first memory cell array and the second memory cell array are embedded in a same memory cell array.

Abstract: A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.

Abstract: A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.

Abstract: A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.

Abstract: A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.

Abstract: A physically unclonable function (PUF) device includes first and second inverters, each of which includes a common gate node and a common drain node. The common drain node of the first inverter is electrically connected to the common gate node of the second inverter. The PUF device also includes a common output node, a first resistive memory device (RMD) electrically connected to the common drain node of the first inverter and the common output node, and a second RMD electrically connected to the common drain node of the second inverter and the common output node.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer. A manufacturing method of a semiconductor structure is also provided.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: A memory device includes a plurality of memory cells. Each of the plurality of memory cells includes a capacitor configured to store an amount of electrical charges, and a plurality of transistors electrically coupled to the capacitor. Based on a pulse signal, a first subset of the plurality of transistors are configured to form a first conduction path, and a second subset of the plurality of transistors are configured to form a second conduction path. The amount of electrical charges is configured to be altered through the first conduction path and the second conduction path.

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Abstract: Some embodiments relate to an integrated circuit including first and second charge-trapping devices and a control circuit. The first charge-trapping device includes a first charge-trapping structure arranged over a substrate between a first gate structure and a first channel region. The second charge-trapping device is coupled in series with the first charge-trapping device and includes a second charge-trapping structure arranged over the substrate between a second gate structure and a second channel region. The control circuit is coupled to the first and second gate structures and is configured to store a first input of an IMPLY operation as a stored value of the first charge-trapping device, store a second input of the IMPLY operation as a stored value of the second charge-trapping device, and update the stored value of the second charge-trapping device based on the stored value of the first charge-trapping device to perform the IMPLY operation.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: A semiconductor device may include a non-volatile memory structure that may be formed in a back end of line (BEOL) region of a semiconductor device. The non-volatile memory structure may include a dielectric-based one-time programmable (OTP) anti-fuse memory structure or a dielectric-based resistive random access memory (ReRAM), among other examples. The non-volatile memory structure may be selectively programmed based on modifying an electrical resistance of the non-volatile memory structure, and may retain data stored in the non-volatile memory structure even when electrical power is removed from the semiconductor device.

Abstract: A semiconductor device includes an array of M inverters, M being an integer of at least 2 such that the array of M inverters includes at least a first inverter and a second inverter; (M?1) pairs of resistive memory devices (RMDs) coupled to the array of M inverters; and a write line coupled to an input of the first inverter. (M?1) inverters of the array of M inverters are each connected in parallel with a pair of RMDs of the (M?1) pairs of RMDs.

Abstract: An embodiment inverter circuit includes an electrically insulating structure having a slab geometry including a first surface and a second surface that are parallel to one another and that are each oriented in respective planes that are perpendicular to a thickness direction, a p-type semiconductor layer formed on the first surface, an n-type semiconductor layer formed on the second surface, a gate dielectric layer formed in contact with the p-type semiconductor layer and the n-type semiconductor layer, a gate electrode formed in contact with the gate dielectric layer, a first source electrode and a first drain electrode formed in contact with the p-type semiconductor layer, and a second source electrode and a second drain electrode formed in contact with the n-type semiconductor layer. The inverter circuit may be connected to a voltage supply, a ground voltage terminal, an input signal terminal, and an output terminal to operate as an inverter.

Abstract: A semiconductor device includes a first gate, a second gate disposed over the first gate, a first contact, a second contact, a third contact disposed between the first gate and the second gate, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer is disposed between the first gate and the third contact. The first semiconductor layer includes a first channel region, a first source region, and a first drain region, and the first channel region laterally extends between the first drain region and the first contact. The second semiconductor layer is disposed between the second gate and the third contact. The second semiconductor layer includes a second channel region, a second source region, and a second drain region, and the second channel region laterally extends between the second drain region and the second contact.

Abstract: A memory device, an operation method of a memory cell in a memory device and a semiconductor die are provided. A computational memory cell in the memory device includes: a field effect transistor (FET), with a changeable threshold voltage; and resistive storage devices, connected by a common terminal coupled to a source/drain terminal of the FET. By altering the threshold voltage of the FET, a logic function of the computational memory cell can be changed. During a logic operation, inputs are provided to the computational memory cell as resistance states of the resistive storage devices, and a current passing through a conduction channel of the FET is functioned as an output for the logic operation.

Abstract: A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Abstract: Various embodiments of the present application are directed towards an integrated circuit including a plurality of semiconductor devices disposed on a substrate. A dielectric structure overlies the semiconductor devices. A plurality of conductive interconnect elements are disposed within the dielectric structure and are electrically coupled to one or more of the semiconductor devices. A data backup unit overlies the plurality of conductive interconnect elements. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer laterally extending over the first and second source/drain structures, a first upper gate structure, and a second upper gate structure. The first and second upper gate structures overlie the channel layer.