Patents by Inventor Yun-Gwan YU

Yun-Gwan YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180276052
    Abstract: A system includes a plurality of hardware blocks, a deadlock detector and an interconnect device. The hardware blocks include a processor executing instructions and a storage device storing data. The deadlock detector monitors operations of a target hardware block among the plurality of hardware blocks in realtime to store debugging information in the storage device. The interconnect device electrically connects the deadlock detector and the plurality of hardware blocks. The interconnect device includes a system bus electrically connecting the plurality of hardware blocks and a debugging bus electrically connecting the deadlock detector to the target hardware block and the storage device. The interconnect device includes a system bus electrically connecting the plurality of hardware blocks and a debugging bus electrically connecting the deadlock detector to the target hardware block and the storage device.
    Type: Application
    Filed: August 7, 2017
    Publication date: September 27, 2018
    Inventors: Jae-Youl KIM, Yun-Gwan YU