Abstract: Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate and drain.

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.