Patents by Inventor Yun-Hee Kim

Yun-Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139616
    Abstract: A multilayer capacitor includes a body including a stack structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes stacked with respective dielectric layers interposed therebetween, external electrodes disposed on external surfaces of the body and connected to the internal electrodes, and an insulating layer covering a surface of the body. One of the external electrodes includes a metal layer connected to the insulating layer, and the insulating layer includes an oxide of a metal component of the metal layer.
    Type: Application
    Filed: May 14, 2021
    Publication date: May 5, 2022
    Inventors: Yun Sung KANG, Min Jung CHO, Yun Hee KIM
  • Patent number: 11322302
    Abstract: A multilayer electronic component includes a body including a dielectric layer and internal electrodes alternately stacked with the dielectric layer interposed therebetween, and an external electrode disposed on the body and connected to the internal electrodes . An end portion of at least one of the internal electrodes in a longitudinal direction of the body is thicker than a central portion of the internal electrode, and a ratio t2/t1 of a thickness t2 of the end portion to a thickness t1 of the central portion satisfies 1.1?t2/t1?1.5.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Suji Kang, Yuhong Oh, Byung Kun Kim, Yun Hee Kim, Min Jung Cho
  • Publication number: 20220090081
    Abstract: The present disclosure relates to novel DNA aptamers and use thereof. In particular, the present disclosure relates to DNA aptamers selected from a DNA library using Cell-SELEX to bind specifically to cancer cells. The DNA aptamers of the present disclosure selected and optimized for high binding affinity to cancer cells can be effectively used for the diagnosis of cancer as they have enhanced targeting efficiencies for target cells and tissues as well as high serum stability.
    Type: Application
    Filed: August 8, 2019
    Publication date: March 24, 2022
    Applicants: JP BIO A INC., NATIONAL CANCER CENTER
    Inventors: Yun Hee KIM, Kyun HEO, Sun II CHOI, In Hoo KIM
  • Patent number: 11244911
    Abstract: A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
  • Publication number: 20210388352
    Abstract: The present invention relates to a pharmaceutical composition for preventing or treating hypertrophic scars. The present inventors have found that the inhibition of expression of TXNDC5, PRRC1, S100A11, Galectin 1, Filamin A, eIF-5A, Annexin A2, and FABP5 can be a new target for improving and treating hypertrophic scars. In the present invention, TXNDC5-, PRRC1-, S100A11-, Galectin 1-, Filamin A-, eIF-5A-, Annexin A2-, and FABP5-specific siRNAs were constructed to determine the probability of treating the hypertrophic scars. As a result, the knockdown of the protein or a gene encoding the protein induces apoptosis in the hypertrophic scars and reduces collagen expression, which can be very useful in treating wounds.
    Type: Application
    Filed: December 4, 2019
    Publication date: December 16, 2021
    Applicant: Tego Science Inc.
    Inventors: SaeWha JEON, Ho Yun CHUNG, Na Ra OH, Yun Hee KIM, Jik Hyon HAN, Hyun Ah MOON
  • Publication number: 20210366837
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Patent number: 11145601
    Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
  • Patent number: 11107773
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Patent number: 11026876
    Abstract: The present invention relates to a composition for skin improvement containing at least one chemokine selected from the group consisting of B lymphocyte chemoattractant (BLC), also known as C-X-C motif ligand 13 (CXCL13), and thymus-expressed chemokine (TECK), also known as C-C motif ligand 25 (CCL25), as an active ingredient. Since the BLC (CXCL13) and TECK (CCL25) of the present invention increase the expression of proliferation marker Ki-67 and collagen IV, which are proteins concerning skin regeneration and skin elasticity, and exhibit excellent melanin-reducing and wound-healing effects and the ability to induce chemotaxis of keratinocytes, they can be applied in a cosmetic composition for skin improvement.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 8, 2021
    Assignee: Tego Science Inc.
    Inventors: Saewha Jeon, Yun Hee Kim, Jik Hyon Han, Hyun Ah Moon
  • Publication number: 20210166875
    Abstract: A multilayer electronic component includes a body including a dielectric layer and internal electrodes alternately stacked with the dielectric layer interposed therebetween, and an external electrode disposed on the body and connected to the internal electrodes . An end portion of at least one of the internal electrodes in a longitudinal direction of the body is thicker than a central portion of the internal electrode, and a ratio t2/t1 of a thickness t2 of the end portion to a thickness t1 of the central portion satisfies 1.1?t2/t1?1.5.
    Type: Application
    Filed: May 5, 2020
    Publication date: June 3, 2021
    Inventors: Suji KANG, Yuhong OH, Byung Kun KIM, Yun Hee KIM, Min Jung CHO
  • Publication number: 20210060153
    Abstract: The present invention relates to a method of preparing an influenza working virus seed stock, a method of increasing infectivity of an influenza working virus seed stock, a method of preparing an influenza vaccine using the seed stock, an influenza vaccine prepared by the method, and an influenza working virus seed stock having increased infectivity.
    Type: Application
    Filed: July 5, 2018
    Publication date: March 4, 2021
    Inventors: Yun Hee KIM, Yong Wook PARK, Dong Soo HAM, Hwan Ui JUNG, Hun KIM
  • Publication number: 20210057278
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10886234
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate which includes a semiconductor chip region and a scribe line region surrounding the semiconductor chip region; an insulating film arranged over the semiconductor chip region and the scribe line region on the substrate, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening portion formed on the second surface of the insulating film and the fourth surface of the insulating film to expose the substrate, wherein the opening portion is formed in the scribe line region, and the first surface of the insulating film and the third surface of the insulating film do not include an opening portion which expose the substrate.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jung Ho Choi
  • Patent number: 10854517
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10811193
    Abstract: A capacitor component includes a porous body, a first electrode layer covering surfaces of pores of the porous body, a dielectric layer covering the first electrode layer, and a second electrode layer filling the pores of the porous body and covering the dielectric layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Hoon Ryou, Hyun Ho Shin, Byeong Cheol Moon, Chang Soo Jang, Tae Joon Park, Yun Hee Kim, Kyo Yeol Lee, Seung Mo Lim
  • Publication number: 20200310016
    Abstract: Provided is a coloring pattern structure. The coloring pattern structure includes: a substrate; a light-transmitting dielectric layer formed on at least one surface of the substrate; and a composite material layer disposed on an upper surface of the light-transmitting dielectric layer and formed of a metal and a first material not having a thermodynamic solid solubility in the metal, wherein the metal included in the composite material layer has a pattern coated only on portions of the upper surface of the light-transmitting dielectric layer, and the first material is coated on the remaining area where the metal is not coated.
    Type: Application
    Filed: November 14, 2019
    Publication date: October 1, 2020
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Ji Young BYUN, So Hye CHO, Seung Yong LEE, Kwang-deok CHOI, In Uk BAEK, Yun Hee KIM
  • Patent number: 10755855
    Abstract: Provided is a capacitor including a substrate including first and second trenches spaced apart from each other, a first electrode disposed in the first trench and one surface of the substrate, a second electrode disposed in the second trench and on the one surface of the substrate and spaced apart from the first electrode, first and second pad electrodes arranged on the first and second electrodes, respectively, and a passivation layer disposed on the first and second pad electrodes and having openings partially exposing the first and second pad electrodes, respectively.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Soo Jang, Yun Hee Kim, Woong Do Jung, Jeong Hoon Ryou
  • Publication number: 20200188272
    Abstract: The present invention relates to a cosmetic composition having a cotton candy form. The cosmetic composition in a cotton candy form is prepared by freeze-drying an algin aqueous solution, and thus can be prepared through a simple process, has excellent moldability, and can stably contain, even at room temperature, a protein such as a cytokine, a peptide, and the like, which have particular storage requirements.
    Type: Application
    Filed: November 22, 2017
    Publication date: June 18, 2020
    Applicant: TEGO SCIENCE INC.
    Inventors: Saewha JEON, Yun Hee KIM, Jikhyon HAN
  • Publication number: 20200168556
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Application
    Filed: June 13, 2019
    Publication date: May 28, 2020
    Inventors: HYUN-SU SIM, YOON-SUNG KIM, YUN-HEE KIM, BYUNG-MOON BAE, JUN-HO YOON
  • Patent number: 10651105
    Abstract: Provided is a semiconductor chip capable of withstanding damage such as cracks created in the fabrication process. A semiconductor chip according to the inventive concept includes: a semiconductor substrate including a residual scribe lane surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, and a cover protection layer formed integrally with a buffering protection layer covering a portion of the residual scribe lane, wherein the buffering protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extending protection layer extending along the residual scribe lane from the corner protection layer and in contact with the cover protection layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hee Kim, Yoon-Sung Kim, Byung-Moon Bae, Hyun-Su Sim