Abstract: A storage device with improved security performance is provided. The storage device comprises a first non-volatile memory storing a firmware image, a second non-volatile memory storing an emergency image, and a storage controller controlling the first and second non-volatile memories, wherein the storage controller checks an integrity of the firmware image received from the first non-volatile memory, loads and executes the emergency image from the second non-volatile memory when the integrity check of the firmware image fails, receives a recover image from an external device based on the emergency image, and provides the recover image to the first non-volatile memory.

Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Abstract: An electronic circuit includes an operator including logic gates configured to perform either one or both of encryption and decryption operations. The electronic circuit further includes a controller configured to control the operator to operate in a first mode in which each of the logic gates outputs a first logic value during a first time period of a clock signal, and operate in a second mode in which a number of first logic gates, each of which outputs the first logic value, among the logic gates, and a number of second logic gates, each of which outputs a second logic value, among the logic gates, are maintained constant during a second time period of the clock signal, in response to a control value indicating that either one or both of the encryption and decryption operations are performed.

Abstract: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation.

Abstract: An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.

Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Abstract: An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.

Abstract: A system on chip includes a central processing unit and a key manager coupled to the central processing unit. The key manager includes a random number generator configured to generate a key and a key memory configured to store the key and a user setting value associated with the key.

Abstract: An electronic circuit includes an operator including logic gates configured to perform either one or both of encryption and decryption operations. The electronic circuit further includes a controller configured to control the operator to operate in a first mode in which each of the logic gates outputs a first logic value during a first time period of a clock signal, and operate in a second mode in which a number of first logic gates, each of which outputs the first logic value, among the logic gates, and a number of second logic gates, each of which outputs a second logic value, among the logic gates, are maintained constant during a second time period of the clock signal, in response to a control value indicating that either one or both of the encryption and decryption operations are performed.

Abstract: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation.

Abstract: A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Abstract: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation.

Abstract: A glitch detector, an electronic device including the glitch detector, and a method of generating an alarm signal are provided. The glitch detector includes a clock generator configured to generate a clock corresponding to a power voltage, a counter configured to count the clock generated by the clock generator and to output a count value, and a comparator configured to compare a reference value with the count value output by the counter and to generate an alarm signal based on a result of the comparison.

Abstract: An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.

Abstract: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation.

Abstract: A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Abstract: A method and apparatus for managing a key for secure storage of data. The apparatus includes a main controller configured to process a command, a cipher unit configured to encrypt a first key to form an encrypted key or encrypt data to form encrypted data based on a result of the main controller processing the command, and decrypt the encrypted key or the encrypted data based on the result of the main controller processing the command, a hash unit configured to hash the first key according to control of the main controller, a decrypted key memory configured to store the first key, and an encrypted key memory configured to store the encrypted key.

Abstract: A system on chip includes a central processing unit and a key manager coupled to the central processing unit. The key manager includes a random number generator configured to generate a key and a key memory configured to store the key and a user setting value associated with the key.

Abstract: A method and apparatus for managing a key for secure storage of data. The apparatus includes a main controller configured to process a command, a cipher unit configured to encrypt a first key to form an encrypted key or encrypt data to form encrypted data based on a result of the main controller processing the command, and decrypt the encrypted key or the encrypted data based on the result of the main controller processing the command, a hash unit configured to hash the first key according to control of the main controller, a decrypted key memory configured to store the first key, and an encrypted key memory configured to store the encrypted key.

Abstract: An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.