Abstract: A method of estimating greenhouse gas emission, performed by a processing device, includes: obtaining at least one time period of a number of working stations for a target manufacturing process of a product; obtaining a number of first power consumption data of the target manufacturing process, wherein the first power consumption data correspond to the working stations respectively; calculating a number of second power consumption data based on the at least one time period and the first power consumption data; searching for a number of target coefficients corresponding to the plurality of working stations respectively in coefficient database based on the target manufacturing process; and calculating greenhouse gas emission data of the target manufacturing process based on the second power consumption data and the target coefficients.

Abstract: A method of fabricating a film vibration device, including: photoetching a surface of a silicon wafer to form a circular-hole array; etching an aluminum layer on the silicon wafer; etching the silicon wafer to form a through-hole array to obtain a porous silicon wafer; attaching a polyethylene terephthalate (PET) sheet to a side of the porous silicon wafer; ablating the PET sheet to obtain a porous PET film; attaching a polyvinylidene fluoride (PVDF) film to a lower side of the porous silicon wafer; performing vacuumization above the porous silicon wafer, while heating the PVDF film below the porous silicon wafer to create dome micro-structures on the PVDF film; and laminating the porous PET film on each of two sides of the PVDF film to obtain the film vibration device. This application also provides a cleaning device having the film vibration device.

Abstract: This application discloses a silicon carbide (SiC)-loaded graphene photocatalyst for hydrogen production under visible light irradiation and a preparation method thereof. Pure SiC and pure black carbon are respectively prepared and mixed to obtain a mixture with a resistance less than 100?. Then the mixture was vacuumized and processed with a current pulse with an increasing voltage until a breakdown occurs, and subjected to ultrasonic stirring, centrifugal washing and vacuum drying in turn to obtain the SiC-loaded graphene photocatalyst. By means of the current pulse, a heterojunction is formed between SiC and graphene to improve the catalytic activity of the photocatalyst; and the photocatalytic hydrogen production rate of SiC nanoparticles can be enhanced after loaded on the graphene.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A method for manufacturing a core-shell coaxial gallium nitride (GaN) piezoelectric nanogenerator is provided. A mask covering a center part of a gallium nitride wafer is removed. An electrodeless photoelectrochemical etching is performed on the gallium nitride wafer to form a primary GaN nanowire array on a surface of the gallium nitride wafer. A precious metal layer provided on the surface of the gallium nitride wafer is removed and an alumina layer is deposited on the surface of the gallium nitride wafer to cover the primary GaN nanowire array to obtain a core-shell coaxial GaN nanowire array. A first conductive layer is provided on a flexible substrate to which the core-shell coaxial GaN nanowire array is transferred. A second conductive layer is provided at a top end of the core-shell coaxial GaN nanowire array, and is connected to an external circuit to obtain the core-shell coaxial GaN piezoelectric nanogenerator.

Abstract: Disclosed are a cocaine esterase mutant and use thereof. The cocaine esterase mutant is obtained by mutating a wildtype cocaine esterase, an amino acid sequence of the wildtype cocaine esterase is shown as SEQ ID No.1, the cocaine esterase mutant is T172R/G173Q/L196C/I301C, or additionally added with V116K point mutation, or additionally added with A51 site mutation, and the A51 site mutation is L, Y, V, F or W. Catalytic efficiency of the cocaine esterase mutant screened on a cocaine toxic metabolite benzoylecgonine is greatly improved compared with that of a wildtype enzyme.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

Abstract: According to implementations of the present disclosure, there is proposed a solution for analyzing a data table in response to a user input. In this solution, a user input in a cell of a data table is determined. The data table comprises a plurality of cells arranged in rows and columns. An analysis operation for the data table is determined based on semantics of the data table and the user input, the analysis operation corresponding to the user input. Further, a result of the analysis operation is presented in a region of the data table related to the cell. In this way, grid characteristics of the data table can be utilized to provide the result of the analysis operation as desired by a user and simple, efficient and user-friendly data analysis can be facilitated.

Abstract: A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Abstract: A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.

Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.