Abstract: A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.

Abstract: A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.

Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.

Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.

Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.

Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.

Abstract: An array circuit substrate including a plurality of substrate units, a plurality of non-stick test circuits, and a plurality of etching windows is provided. Each of the substrate units has a plurality of wire-bond pads and a plurality of plated wires. One of the plated wires is connected to one of the corresponding wire-bond pads, and at least one of the plated wires is a test wire. The non-stick test circuits are respectively disposed between two adjacent substrate units. Each test wire is connected to a test point through the non-stick test circuits. The etching windows are located on the substrate units. The plated wires are respectively cut by the etching windows except the test wires. Furthermore, the non-stick test circuits are not cut by the etching windows.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.

Abstract: A flip-chip package substrate with a high-density layout. A number of pads and a number of traces are formed on an upper surface of the substrate. At least a pad has a short axis and a vertical long axis which are perpendicular to each other. The distance between the elongated pad and the pad adjacent thereto is not smaller than two thirds of the length of the short axis, so that at least two of the traces can pass between the elongated pad and the pad adjacent thereto.

Abstract: A BGA package comprises a chip with an array pad design disposed on the top surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. All of the power supply pads and ground pads are adjacent to one another and designed in the outer row of the bonding pads, and the I/O pads are designed in the outer row, the middle row and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively.

Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: A BGA package comprises a chip with an array pad design disposed on the top surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. All of the power supply pads and ground pads are adjacent to one another and designed in the outer row of the bonding pads, and the I/O pads are designed in the outer row, the middle row and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively.