Patents by Inventor Yun Hsiang Tien

Yun Hsiang Tien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9219048
    Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: December 22, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yun-Hsiang Tien, Yi-Chuan Ding
  • Publication number: 20140367852
    Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 18, 2014
    Inventors: Yun-Hsiang TIEN, Yi-Chuan DING
  • Patent number: 8089164
    Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 3, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ko-Wei Lin, Yun-Hsiang Tien, Kun-Ting Hung
  • Publication number: 20100176516
    Abstract: The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.
    Type: Application
    Filed: September 23, 2009
    Publication date: July 15, 2010
    Inventors: Ko-Wei Lin, Yun-Hsiang Tien, Kun-Ting Hung
  • Publication number: 20070152348
    Abstract: An array circuit substrate including a plurality of substrate units, a plurality of non-stick test circuits, and a plurality of etching windows is provided. Each of the substrate units has a plurality of wire-bond pads and a plurality of plated wires. One of the plated wires is connected to one of the corresponding wire-bond pads, and at least one of the plated wires is a test wire. The non-stick test circuits are respectively disposed between two adjacent substrate units. Each test wire is connected to a test point through the non-stick test circuits. The etching windows are located on the substrate units. The plated wires are respectively cut by the etching windows except the test wires. Furthermore, the non-stick test circuits are not cut by the etching windows.
    Type: Application
    Filed: September 11, 2006
    Publication date: July 5, 2007
    Inventors: Ying-Chih Chen, Yun-Hsiang Tien
  • Patent number: 7125745
    Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 24, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kun-Ching Chen, Yi-Chuan Ding, Po-Jen Cheng, Chih-Ming Chung, Yun-Hsiang Tien
  • Patent number: 7091583
    Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 15, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ying-Chih Chen, Yun-Hsiang Tien, Ming-Jiun Lai, Yi-Chuan Ding
  • Publication number: 20050248037
    Abstract: A flip-chip package substrate with a high-density layout. A number of pads and a number of traces are formed on an upper surface of the substrate. At least a pad has a short axis and a vertical long axis which are perpendicular to each other. The distance between the elongated pad and the pad adjacent thereto is not smaller than two thirds of the length of the short axis, so that at least two of the traces can pass between the elongated pad and the pad adjacent thereto.
    Type: Application
    Filed: May 6, 2005
    Publication date: November 10, 2005
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Pin Hung, Pao-Nan Li, Hsueh-Te Wang, Yun-Hsiang Tien
  • Patent number: 6921981
    Abstract: A BGA package comprises a chip with an array pad design disposed on the top surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. All of the power supply pads and ground pads are adjacent to one another and designed in the outer row of the bonding pads, and the I/O pads are designed in the outer row, the middle row and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: July 26, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Yun Hsiang Tien
  • Publication number: 20050051881
    Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 10, 2005
    Inventors: Ying-Chih Chen, Yun-Hsiang Tien, Ming-Jiun Lai, Yi-Chuan Ding
  • Publication number: 20040212088
    Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.
    Type: Application
    Filed: April 28, 2004
    Publication date: October 28, 2004
    Applicant: Advanced Semiconductor Engineering Inc.
    Inventors: Kun-Ching Chen, Yi-Chuan Ding, Po-Jen Cheng, Chih-Ming Chung, Yun-Hsiang Tien
  • Publication number: 20030127731
    Abstract: A BGA package comprises a chip with an array pad design disposed on the top surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. All of the power supply pads and ground pads are adjacent to one another and designed in the outer row of the bonding pads, and the I/O pads are designed in the outer row, the middle row and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively.
    Type: Application
    Filed: January 3, 2003
    Publication date: July 10, 2003
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yun-Hsiang Tien