Abstract: A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.

Abstract: A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract: A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.

Abstract: A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.

Abstract: A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.

Abstract: Preferred embodiments of the present invention utilize system-level band gap engineering. Device improving structures, such as the strained source/drain regions for PMOS devices and a tensile film for NMOS devices, may be employed only in those selected regions such as where high drive current is necessary or desirable. In other regions of the integrated circuit, where high drive current is not a concern, conventional structures may be employed. In preferred embodiments, SiGe is employed for increasing the carrier mobility for PMOS devices. Preferably, the SiGe layer is located at source/drain regions, junction, or inside the channel region. Likewise, a tensile stress imposing film, preferably a silicon nitride film and more preferably a silicon nitride contact etch stop layer deposited using a plasma deposition technique, may be employed in those NMOS devices and device regions wherein enhanced electron mobility is necessary or desired.

Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

Abstract: A method for inline monitoring of a device's pattern profile is disclosed. An insulator is deposited on the patterned layer to be detected by high density plasma chemical vapor deposition. A defect measurement device or refraction measurement device is used to compare the difference of the insulator in nearby dies in corresponding local areas. The insulator deposited on the patterned layer reflects the abnormal pattern profile (such as under cut, footing, or taper) and the normal pattern profile of the patterned layer. Thus, the abnormal pattern profile can be detected and qualified by defect measurement or refraction measurement devices.

Abstract: A method of etching a dielectric layer employs steps of: providing a silicon substrate with a surface covered by the dielectric layer; polymer-rich plasma etching to remove part of the dielectric layer and form a polymer film on the exposed regions of the dielectric layer and the silicon substrate; performing an oxygen plasma treatment on the polymer film; and wet etching to completely remove the polymer film.