Patents by Inventor Yun Hyuck Ji

Yun Hyuck Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11877437
    Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Beom Ho Mun, Eun Jeong Kim, Jong Kook Park, Seung Mi Lee, Ji Won Choi, Kyoung Tak Kim, Yun Hyuck Ji
  • Publication number: 20230009388
    Abstract: A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.
    Type: Application
    Filed: January 4, 2022
    Publication date: January 12, 2023
    Inventor: Yun Hyuck JI
  • Patent number: 11545494
    Abstract: A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Ho Mun, In-Sang Kim
  • Publication number: 20220059543
    Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.
    Type: Application
    Filed: July 13, 2021
    Publication date: February 24, 2022
    Inventors: Beom Ho MUN, Eun Jeong KIM, Jong Kook PARK, Seung Mi LEE, Ji Won CHOI, Kyoung Tak KIM, Yun Hyuck JI
  • Patent number: 10978458
    Abstract: A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Ho Mun, In-Sang Kim
  • Publication number: 20210035984
    Abstract: A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Inventors: Yun-Hyuck JI, Beom-Ho MUN, In-Sang KIM
  • Patent number: 10847519
    Abstract: A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Ho Mun, In-Sang Kim
  • Publication number: 20200266198
    Abstract: A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Yun-Hyuck JI, Beom-Ho MUN, In-Sang KIM
  • Patent number: 10672773
    Abstract: A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Ho Mun, In-Sang Kim
  • Publication number: 20190296024
    Abstract: A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.
    Type: Application
    Filed: November 16, 2018
    Publication date: September 26, 2019
    Inventors: Yun-Hyuck JI, Beom-Ho MUN, In-Sang KIM
  • Publication number: 20190296026
    Abstract: A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.
    Type: Application
    Filed: November 16, 2018
    Publication date: September 26, 2019
    Inventors: Yun-Hyuck JI, Beom-Ho MUN, In-Sang KIM
  • Patent number: 9899518
    Abstract: A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 20, 2018
    Assignee: SK Hynix Inc.
    Inventor: Yun-Hyuck Ji
  • Patent number: 9659828
    Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 23, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Yong Kim, Seung-Mi Lee
  • Publication number: 20170110457
    Abstract: A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventor: Yun-Hyuck JI
  • Patent number: 9570608
    Abstract: A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 14, 2017
    Assignee: SK Hynix Inc.
    Inventor: Yun-Hyuck Ji
  • Patent number: 9548304
    Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 17, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Patent number: 9520495
    Abstract: A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: December 13, 2016
    Assignee: SK HYNIX INC.
    Inventor: Yun-Hyuck Ji
  • Patent number: 9431402
    Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: August 30, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun-Hyuck Ji, Kwan-Woo Do, Beom-Yong Kim, Seung-Mi Lee, Woo-Young Park
  • Patent number: 9406678
    Abstract: A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 2, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Moon-Sig Joo, Se-Aug Jang, Seung-Mi Lee, Hyung-Chul Kim
  • Publication number: 20160211183
    Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Inventors: Yun-Hyuck JI, Beom-Yong KIM, Seung-Mi LEE