Patents by Inventor Yun Je Choi
Yun Je Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963311Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.Type: GrantFiled: March 25, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jae Woong Choi, Yun Je Ji, Seung Eun Lee, Yong Hoon Kim
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Publication number: 20230178854Abstract: The present invention relates to a method for manufacturing a polyimide-powder composite separator using water and a polyimide-powder composite separator manufactured by the method, and is environmentally friendly since an organic solvent is not used in the overall process of manufacturing the composite separator and has advantageous effects in terms of time, cost, and manufacturing process since a high temperature/high pressure environment is not required.Type: ApplicationFiled: October 11, 2022Publication date: June 8, 2023Inventors: Seungwon SONG, Chan Moon CHUNG, Yun Je CHOI, Hyun Soo AN, Seung Won JIN, Seung Hyun LEE, Jun Seo LEE, Dam Bi KIM, Ji Sun LEE, Hyun Woo KIM, Kang Hoon YOON
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Patent number: 11296088Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: July 24, 2019Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Patent number: 10490446Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.Type: GrantFiled: November 1, 2017Date of Patent: November 26, 2019Assignee: SK hynix Inc.Inventors: Hae-Jung Park, Jung-Taik Cheong, Tae-Woo Jung, Yun-Je Choi
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Publication number: 20190348418Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: July 24, 2019Publication date: November 14, 2019Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 10411014Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: July 15, 2016Date of Patent: September 10, 2019Assignee: SK hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Publication number: 20180122898Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.Type: ApplicationFiled: November 1, 2017Publication date: May 3, 2018Inventors: Hae-Jung PARK, Jung-Taik CHEONG, Tae-Woo JUNG, Yun-Je CHOI
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Patent number: 9837490Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.Type: GrantFiled: January 13, 2016Date of Patent: December 5, 2017Assignee: SK Hynix Inc.Inventors: Hae-Jung Park, Jung-Taik Cheong, Tae-Woo Jung, Yun-Je Choi
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Publication number: 20170005166Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.Type: ApplicationFiled: January 13, 2016Publication date: January 5, 2017Inventors: Hae-Jung PARK, Jung-Taik CHEONG, Tae-Woo JUNG, Yun-Je CHOI
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Publication number: 20160329337Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 9425200Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: October 16, 2014Date of Patent: August 23, 2016Assignee: SK Hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Publication number: 20150126013Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: October 16, 2014Publication date: May 7, 2015Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 7674711Abstract: The present invention relates to a method of fabricating a flash memory device. The method may include forming a first and a second interlayer insulating film on a semiconductor substrate having a cell region, etching the second and first interlayer insulating films, thus forming a contact hole through which a junction region of the cell region is exposed, forming a contact plug within the contact hole, the contact plug having a height lower than that of an interface of the first and second interlayer insulating films, and forming a spacer on sidewalls of the contact hole over the contact plug.Type: GrantFiled: December 6, 2007Date of Patent: March 9, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Yun Je Choi
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Publication number: 20090184426Abstract: The contact plugs of a semiconductor device includes first contact plugs having an elliptical sectional shape, and second contact plugs formed on the first contact plugs and having a circular sectional shape. The second contact plugs being configured to come in contact with the first contact plugs, thereby preventing voids from being formed.Type: ApplicationFiled: June 27, 2008Publication date: July 23, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Yun Je CHOI
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Publication number: 20090068833Abstract: The present invention relates to a method of forming a contact hole of a semiconductor device. According to the method of forming a contact hole of a semiconductor device, a semiconductor substrate in which gates and junctions are formed is provided. A self-aligned contact (SAC) nitride layer is formed on a surface of the gates. A pre-metal dielectric layer is formed on the SAC nitride layer. A contact hole is formed to thereby expose the junction between the gates. A passivation layer is formed on sidewalls of the contact hole. A contact plug is formed, thus gap-filling the contact hole.Type: ApplicationFiled: June 27, 2008Publication date: March 12, 2009Applicant: Hynix Semiconductor Inc.Inventor: Yun Je Choi
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Publication number: 20090004854Abstract: The present invention relates to a method of fabricating a flash memory device. The method may include forming a first and a second interlayer insulating film on a semiconductor substrate having a cell region, etching the second and first interlayer insulating films, thus forming a contact hole through which a junction region of the cell region is exposed, forming a contact plug within the contact hole, the contact plug having a height lower than that of an interface of the first and second interlayer insulating films, and forming a spacer on sidewalls of the contact hole over the contact plug.Type: ApplicationFiled: December 6, 2007Publication date: January 1, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Yun Je Choi