Patents by Inventor Yun-Ju Sun

Yun-Ju Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with strained layer
    Patent number: 9831321
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
  • Semiconductor Device with Strained Layer
    Publication number: 20160293735
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
  • Semiconductor device with strained layer
    Patent number: 9368626
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
  • Semiconductor Device with Strained Layer
    Publication number: 20150155383
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
  • Structure and method for MOSFETS with high-K and metal gate structure
    Patent number: 8912610
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr Jung Lin, Yun-Ju Sun, Shih-Hsun Chang, Chia-Jen Chen, Tomonari Yamamoto, Chih-Wei Kuo, Meng-Yi Sun, Kuo-Chiang Ting
  • Structure and Method for MOSFETS with High-K and Metal Gate Structure
    Publication number: 20130119487
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.
    Type: Application
    Filed: April 3, 2012
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jr Jung Lin, Yun-Ju Sun, Shih-Hsun Chang, Chia-Jen Chen, Tomonari Yamamoto, Chih-Wei Kuo, Meng-Yi Sun, Kuo-Chiang Ting