Patents by Inventor Yun-Jui Hsieh

Yun-Jui Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power MOSFET package
    Patent number: 8410599
    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 2, 2013
    Inventors: Baw-Ching Perng, Ying-Nan Wen, Shu-Ming Chang, Ching-Yu Ni, Yun-Jui Hsieh, Wei-Ming Chen, Chia-Lun Tsai, Chia-Ming Cheng
  • POWER MOSFET PACKAGE
    Publication number: 20100289092
    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat
    Type: Application
    Filed: April 8, 2010
    Publication date: November 18, 2010
    Inventors: Baw-Ching PERNG, Ying-Nan Wen, Shu-Ming Chang, Ching-Yu Ni, Yun-Jui Hsieh, Wei-Ming Chen, Chia-Lun Tsai, Chia-Ming Cheng