Abstract: An ink-jet printhead and a method for manufacturing the same utilize coating a first photosensitive photoresist on the substrate and forming a passage plate, forming an ink chamber and an ink passage on the passage plate, burying the ink chamber and the ink passage using a second photoresist and forming a mold layer, forming a chamber cover layer on a top surface of the passage plate and the mold layer, forming a plurality of slots corresponding to the ink chamber and/or the ink passage in the chamber cover layer, supplying an etchant to the second photoresist through the slots and removing the second photoresist remaining in the ink chamber and the ink passage, and coating a third photoresist and forming a nozzle plate on the chamber cover layer.

Abstract: A capacitor in a semiconductor integrated circuit, and a method for fabricating the capacitor is disclosed. A method of an embodiment of the invention includes first providing a semiconductor substrate having disposed thereon an interlayer insulating layer. A lower sacrificial insulating layer and an upper etching stopper layer then are sequentially formed on the interlayer insulating layer on the semiconductor substrate. The upper etching stopper layer and the lower sacrificial insulating layer then are sequentially patterned to form a storage electrode hole, and to expose a predetermined portion of the interlayer insulating layer. The method then includes forming an outer cylindrical storage electrode in the storage electrode hole, a conductive liner surrounded by the outer cylindrical storage electrode, and an inner storage electrode surrounded by the conductive liner.

Abstract: Noise is introduced into test inputs and voltage supplies provided to logic devices while under going testing by modulating a test voltage output with a noise signal to produce the test input. In particular, a noise signal and a test voltage output are generated. The test voltage output is modulated with the noise signal to provide a test input to the logic device. A more accurate approximation of an actual operating environment is thereby provided.

Abstract: This invention provides a method for manufacturing a this film transistor which comprised the steps of providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, the first channel layer, the second polysilicon laye

Abstract: This invention provides a method for manufacturing a thin film transistor which comprised the steps of providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, the first channel layer, the second polysilicon laye