Patents by Inventor Yun Kil Kim

Yun Kil Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366173
    Abstract: The present invention relates to a device of simultaneous interpretation based on real-time extraction of an interpretation unit, the device including a voice recognition module configured to recognize voice units as sentence units or translation units from vocalized speech that is input in real time, a real-time interpretation unit extraction module configured to form one or more of the voice units into an interpretation unit, and a real-time interpretation module configured to perform an interpretation task for each interpretation unit formed by the real-time interpretation unit extraction module.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 30, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chang Hyun Kim, Young Kil Kim, Yun Keun Lee
  • Patent number: 10332033
    Abstract: An incremental self-learning based dialogue apparatus for dialogue knowledge includes a dialogue processing unit configured to determine a intention of a user utterance by using a knowledge base and perform processing or a response suitable for the user intention, a dialogue establishment unit configured to automatically learn a user intention stored in a intention annotated learning corpus, store information about the learned user intention in the knowledge base, and edit and manage the knowledge base and the intention annotated learning corpus, and a self-knowledge augmentation unit configured to store a log of a dialogue performed by the dialogue processing unit, detect and classify an error in the stored dialogue log, automatically tag a user intention for the detected and classified error, and store the tagged user intention in the intention annotated learning corpus.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 25, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Oh Woog Kwon, Young Kil Kim, Yun Keun Lee
  • Patent number: 9653160
    Abstract: A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Kil Kim, Jeong-Yun Cha
  • Publication number: 20160148682
    Abstract: A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals.
    Type: Application
    Filed: August 11, 2015
    Publication date: May 26, 2016
    Inventors: YUN-KIL KIM, Jeong-Yun Cha
  • Patent number: 9245651
    Abstract: A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output block is configured to mask bits having a logic level among the plurality of data bits in the read data to output the masked read data to the plurality of input/output pins.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: January 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Yun Cha, Yun Kil Kim, Jeong Hwa Jeong
  • Publication number: 20150016200
    Abstract: A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output block is configured to mask bits having a logic level among the plurality of data bits in the read data to output the masked read data to the plurality of input/output pins.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 15, 2015
    Inventors: JEONG YUN CHA, Yun Kil Kim, Jeong Hwa Jeong