Patents by Inventor Yun Li

Yun Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183622
    Abstract: A micro light-emitting device module includes a circuit substrate, a planarization layer and a micro light-emitting device. The planarization layer is disposed on an upper surface of the circuit substrate and has a first surface and a second surface opposite to each other. The second surface is in contact with the upper surface of the circuit substrate. The micro light-emitting device is disposed on the first surface of the planarization layer. A maximum height difference of the second surface of the planarization layer is greater than a thickness of the micro light-emitting device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 23, 2021
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Yu-Hung Lai, Pei-Hsin Chen, Yi-Chun Shih
  • Publication number: 20210342261
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • Patent number: 11163192
    Abstract: A display apparatus including a first display surface and a second display surface opposite to each other is provided. The display apparatus includes a reflective display panel and a micro light-emitting diode (LED) panel. The reflective display panel is provided with the first display surface and a visible light transmittance of the reflective display panel is higher than 30%. The micro LED panel is disposed overlapping with the reflective display panel and provided with the second display surface. The micro LED panel includes a drive circuit layer and a plurality of micro LED elements. The drive circuit layer is located between the reflective display panel and the second display surface. The micro LED elements are electrically bonded to the drive circuit layer. A visible light transmittance of the micro LED panel is higher than 50%.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 2, 2021
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yun-Li Li, Kuan-Yung Liao
  • Publication number: 20210332845
    Abstract: The present disclosure provides a flexible hinge structure including: a rigid driving member; a mounting fixed member which is connected to an upper surface of the rigid driving member through a first flexible portion at one end in a longitudinal direction of the upper surface, a first fixing structure being provided on a surface of the mounting fixed member; a displacement output member connected to the upper surface of the rigid driving member through a second flexible portion at the other end in the longitudinal direction of the upper surface; and a pair of guiding fixed members symmetrically disposed on both sides of the displacement output member through third flexible portions, the both sides being parallel to the longitudinal direction of the upper surface of the rigid driving member and a second fixing structure being provided on a surface of each of the guiding fixed members.
    Type: Application
    Filed: December 27, 2018
    Publication date: October 28, 2021
    Applicant: The Institute of Optics and Electronics, The Chinese Academy of Sciences
    Inventors: Taotao FU, Yun LI
  • Patent number: 11157193
    Abstract: A write request to program data to a memory device of a memory sub-system is received. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request to read the data from the memory device is received and a look-up operation of the data structure is performed to identify the intermediate entry. Using the pointer to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request and the read request is executed using the read buffer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 26, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Peng Xu, Jiangang Wu, Yun Li
  • Publication number: 20210318142
    Abstract: Methods, apparatus, and systems for estimating and calibrating a gyroscope's scale using a magnetometer mounted on the same device by rotating the device about an axis multiple times; and, during the first rotation, storing the magnetometer magnetic field reading and a heading (from integration of the gyroscope readings) at each of a plurality of angular reference points; then, during each subsequent rotation, determining magnetometer/gyroscope-heading output pairs for which the magnetometer output matches the magnetometer reading corresponding to one of the reference points, thereby indicating that the device has reached the same heading as the matching reference point; then, for each matching output sample pair, using that magnetometer/gyroscope-heading output sample pair to update the gyroscope scale factor for the corresponding angular reference point; and averaging those scale estimates to generate a final gyroscope scale factor estimate.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventors: Bryan A. Cook, Yun Li, Mark Turner
  • Patent number: 11138115
    Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yun Li
  • Patent number: 11137657
    Abstract: A display apparatus including an electrically-controlled phase retardation layer, a reflective polarizer, a micro light emitting diode panel and a reflective layer is provided. The electrically-controlled phase retardation layer has a first side and a second side opposite to each other. The reflective polarizer is disposed at the first side of the electrically-controlled phase retardation layer. The micro light emitting diode panel is disposed at the second side of the electrically-controlled phase retardation layer and includes a circuit substrate and a plurality of micro light emitting diodes. The reflective layer is disposed between the reflective polarizer and the circuit substrate. An orthogonal projection of the reflective layer on the circuit substrate is not overlapped with orthogonal projections of the micro light emitting diodes on the circuit substrate.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: October 5, 2021
    Assignee: PlayNitride Display Co., Ltd.
    Inventor: Yun-Li Li
  • Patent number: 11136548
    Abstract: Described herein are cell culture media useful for the differentiation of human pluripotent stem cells into microglia. The methods described herein relate to in vitro generation of expandable, bankable, microglial cells by directed differentiation from human pluripotent stem cells (induced or embryonic). Using only defined cell culture media, differentiation of pluripotent stem cells is directed down a mesodermal path, in a rapid and scalable fashion, to generate cells adopting signatures of their in vivo counterparts, including gene expression, protein marker expression and functionality.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 5, 2021
    Assignee: Whitehead Institute for Biomedical Research
    Inventors: Julien Muffat, Yun Li, Rudolf Jaenisch
  • Patent number: 11137943
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20210303340
    Abstract: Methods, systems, and devices for a read counter for quality of service design are described. First commands may be assigned to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level. The memory die may include a second queue associated with a second priority level different from the first priority level, the second queue comprising one or more second commands assigned. Based at least in part on a counter associated with the first queue and the first and second priority levels, it may be determined that a threshold number of the first commands of the first queue have issued without a command from the one or more second commands having issued. A command from the second commands may issue before issuing a next command of the first commands based at least in part on the counter.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Yun Li, Jiangang Wu, James P. Crowley
  • Publication number: 20210294522
    Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Inventors: Mark Ish, Yun Li, Scheheresade Virani, John Paul Traver, Ning Zhao
  • Patent number: 11127341
    Abstract: A light emitting module including a circuit carrier and a plurality of light emitting devices is provided. The circuit carrier includes a first circuit layer, a second circuit layer, a dielectric layer and a plurality of conductive vias. The first circuit layer and the second circuit layer are located at two opposite sides of the dielectric layer. The conductive vias pass through the dielectric layer and two opposite end portions of each of the conductive vias are respectively connected to the first circuit layer and the second circuit layer. The light emitting devices are electrically bonded to the first circuit layer. Moreover, the light emitting devices are disposed in a device disposing area of the circuit carrier and the conductive vias are arranged outside the device disposing area. A display device is also provided.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 21, 2021
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Yu-Hung Lai, Po-Jen Su, Hsuan-Wei Mai
  • Publication number: 20210287750
    Abstract: Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Jiangang Wu, James P. Crowley, Yun Li
  • Patent number: 11120099
    Abstract: Rendering a web element in a web page in an integrated development environment is provided. A reference address is extracted from code of a web page. The reference address references a web element. The web element is obtained based on the reference address and in response to the reference address indicating that the web element is an embedded web element. The web element is added to a resource pool. The web element of the resource pool is rendered in the web page.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 14, 2021
    Assignee: International Business machines Corporation
    Inventors: Na Dong, David L. Kaminsky, Yun Li Li, Xi Ning Wang, Rui Yin
  • Publication number: 20210278976
    Abstract: Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: Yun Li, John Traver
  • Publication number: 20210282281
    Abstract: A dual display device is provided, which includes a housing, a first display screen, a flexible display screen, and a rotating assembly. The housing includes a plurality of vertical walls and a bottom wall, the plurality of vertical walls include a second vertical wall. The first display screen is mounted in the housing at a first predetermined distance from the bottom wall, and a first edge of the first display screen is spaced apart from the second vertical wall by a second predetermined distance. The rotating assembly is rotatably disposed in an opening in an axial direction of the rotating assembly.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 9, 2021
    Applicant: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yun LI, Xuesi QIN
  • Publication number: 20210279176
    Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventor: Yun Li
  • Publication number: 20210278995
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20210278985
    Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: John Paul Traver, Yun Li, Scheheresade Virani, Ning Zhao, Tom Victor Maria Geukens