Patents by Inventor Yun-Liang Ouyang

Yun-Liang Ouyang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8304570
    Abstract: A prepolymer for biomedical materials has the following formula: wherein X1 represents aliphatic compounds or aromatic compounds, X3 represents alkene-containing compounds, and X2 represents siloxane compounds having the following formula. In one embodiment of the present invention, n is between 1 and 20, m is between 10 and 20, and y is between 1 and 7.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 6, 2012
    Inventors: Yun Liang Ouyang, Chih Hung Chang
  • Patent number: 8303382
    Abstract: A polishing pad, comprising a mounting surface and an opposing polishing surface with a polishing pattern having at least one aperture thereon, is formed with an adhesive layer adhered to the mounting surface with uniform adhesive strength therebetween. Embodiments include applying an adhesive layer to the mounting surface with uniform pressure prior to forming the polishing pattern on the polishing surface. Embodiments also include forming the polishing pattern having at least one aperture, forming a fitter having a surface pattern opposite to the polishing pattern and having a projection, positioning the fitter on the polishing pattern so that the projection fills the aperture in the polishing pattern forming a composite having substantially parallel opposing surfaces, applying pressure to bond the adhesive layer to the mounting surface with substantially uniform adhesive strength therebetween, and removing the fitter.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: November 6, 2012
    Assignee: IV Technologies Co., Ltd.
    Inventors: Yu-Piao Wang, Yun-Liang Ouyang
  • Publication number: 20100286428
    Abstract: A prepolymer for biomedical materials has the following formula: wherein X1 represents aliphatic compounds or aromatic compounds, X3 represents alkene-containing compounds, and X2 represents siloxane compounds having the following formula. In one embodiment of the present invention, n is between 1 and 20, m is between 10 and 20, and y is between 1 and 7.
    Type: Application
    Filed: February 12, 2010
    Publication date: November 11, 2010
    Inventors: YUN LIANG OUYANG, CHIH HUNG CHANG
  • Publication number: 20070093191
    Abstract: A polishing pad, comprising a mounting surface and an opposing polishing surface with a polishing pattern having at least one aperture thereon, is formed with an adhesive layer adhered to the mounting surface with uniform adhesive strength therebetween. Embodiments include applying an adhesive layer to the mounting surface with uniform pressure prior to forming the polishing pattern on the polishing surface. Embodiments also include forming the polishing pattern having at least one aperture, forming a fitter having a surface pattern opposite to the polishing pattern and having a projection, positioning the fitter on the polishing pattern so that the projection fills the aperture in the polishing pattern forming a composite having substantially parallel opposing surfaces, applying pressure to bond the adhesive layer to the mounting surface with substantially uniform adhesive strength therebetween, and removing the fitter.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 26, 2007
    Inventors: Yu-Piao Wang, Yun-Liang Ouyang
  • Patent number: 6979367
    Abstract: A method of improving surface planarity of a wafer. The method includes forming a first thin-film layer on the wafer using CVD in a first thin film deposition apparatus having at least one gas injector, relative to which the wafer has a first orientation, and forming a second thin-film layer on the wafer using CVD. The second deposition takes place in a second thin film deposition apparatus having at least one second gas injector arranged the same as that in the first thin film deposition apparatus, the wafer having a second orientation relative to the gas injector in the second thin film deposition apparatus. A first angle between the two orientations results in the second apparatus' injector distributing material in a different area from that of the first gas injector.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: December 27, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ching Chan, Yun-Liang Ouyang, Yung-Wei Lu
  • Publication number: 20050037616
    Abstract: A method of improving surface planarity of a wafer. The method includes forming a first thin-film layer on the wafer using CVD in a first thin film deposition apparatus having at least one gas injector, relative to which the wafer has a first orientation, and forming a second thin-film layer on the wafer using CVD. The second deposition takes place in a second thin film deposition apparatus having at least one second gas injector arranged the same as that in the first thin film deposition apparatus, the wafer having a second orientation relative to the gas injector in the second thin film deposition apparatus. A first angle between the two orientations results in the second apparatus' injector distributing material in a different area from that of the first gas injector.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 17, 2005
    Inventors: Chien-Ching Chan, Yun-Liang Ouyang, Yung-Wei Lu
  • Publication number: 20020168848
    Abstract: The present invention provides a method of fabricating an interconnect structure. First, a semiconductor substrate comprising a conductive region containing a metal line and a hole is provided. Next, a titanium layer is formed on the semiconductor substrate. Next, a first titanium nitride layer is formed on the titanium layer by chemical vapor deposition. Finally, a second titanium nitride layer is formed on the first titanium nitride layer by physical vapor deposition.
    Type: Application
    Filed: August 21, 2001
    Publication date: November 14, 2002
    Inventors: Yun-Liang Ouyang, Chao-Yuan Huang
  • Publication number: 20020055202
    Abstract: The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substrate having raised portions and recessed portions; forming a first etch stop layer covering the raised portions and the recessed portions; forming a dielectric layer covering an upper surface of the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of each of the raised portions; forming a second etch stop layer covering the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer on an upper surface of the raised portions, and remaining a plurality of remaining portions of the second etch stop layer on the planarized surface, and remaining the dielectric layer between raised portions.
    Type: Application
    Filed: August 15, 2001
    Publication date: May 9, 2002
    Inventors: Chih-Sheng Yang, Kuei-Chang Tsai, Chih-Hung Shu, Yun-Liang Ouyang
  • Patent number: 6384482
    Abstract: The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substrate having raised portions and recessed portions; forming a first etch stop layer covering the raised portions and the recessed portions; forming a dielectric layer covering an upper surface of the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of each of the raised portions; forming a second etch stop layer covering the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer on an upper surface of the raised portions, and remaining a plurality of remaining portions of the second etch stop layer on the planarized surface, and remaining the dielectric layer between raised portions.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: May 7, 2002
    Assignee: Mosel Vitelic Inc.
    Inventors: Chih-Sheng Yang, Kuei-chang Tsai, Chih-hung Shu, Yun-liang Ouyang
  • Patent number: 6336787
    Abstract: A wafer transfer method using a robot arm for sucking the front-side of the uppermost one of a plurality of wafers stored in a cassette, and for transferring the wafer having a tape adhered to the front-side thereof to a semiconductor tape-peeling device for tape-peeling. Although the wafer warps, the undesired effect that the robot arm crashes any of the wafers can be avoided by using this method.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: January 8, 2002
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chin-hsiang Chang, Yun-liang Ouyang, Chih-shen Yang, Kuei-chang Tsai
  • Patent number: 6117780
    Abstract: The present invention discloses a chemical mechanical polishing method with in-line thickness detection. First, the semiconductor wafer is loaded into CMP equipment and is putted on a loading table for the preparation of a CMP process. The CMP process is performed on the wafer for polishing. The CMP process is interrupted and the thickness of a polished thin film layer is detected by using an in-line thickness measurement technique. The thickness is determined whether or not being accepted by a specification of the CMP process. As the thickness is accepted by the specification, the wafer is cleaned, dried and moved out from the CMP equipment. Alternatively, the thickness is not accepted by the specification, it must be determined whether or not the thickness is less than the low limit of the specification. As the thickness is smaller than the low limit, the wafer is cleaned, dried after it is moved out from the CMP equipment.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: September 12, 2000
    Assignee: Mosel Vitelic Inc.
    Inventors: Kuei-Chang Tsai, Chin-Hsiang Chang, Li-Chun Hsien, Yun-Liang Ouyang