Abstract: Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer without using a separate insulating layer formed on the molding layer as in the conventional art.

Abstract: Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer without using a separate insulating layer formed on the molding layer as in the conventional art.

Abstract: Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.

Abstract: Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.

Abstract: There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved.

Abstract: There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.

Abstract: A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.

Abstract: There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved.

Abstract: There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.