Abstract: A method and apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus. The FIFO buffer having a first port connected to the first bus and a second port connected to the second bus. The apparatus further includes a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch.

Abstract: Apparatus and an accompanying method for implementing a communications protocol for use in generally a distributed, and particularly a highly parallel, multi-processing system (5), for communicating application data of arbitrarily varying strides between separate processors and generally without the need for intermediate data storage. Specifically, application data is transferred through a succession of packets (770) between originating and destination application programs (252), with each packet containing a partial data message. Each partial data message contains a portion of the data that is stored in a stride one portion of an originating application data memory (700). Upon reception, each data portion is written into a stride one portion of a destination application data memory (760). An application interface (254), executing independently at both the originating and destination processing elements (10.sub.1, 10.sub.