Patents by Inventor Yun-rae Cho
Yun-rae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088082Abstract: A semiconductor package, including a substrate extending in first direction and a second direction intersecting the first direction and including a solder resist layer having an open area thereon; a semiconductor chip on the substrate in a third direction, the third direction intersecting the first direction and the second direction, a first surface of the semiconductor chip facing the substrate; and a bump structure in contact with a first connection pad on the open area and a second connection pad on the first surface of the semiconductor chip, and configured to connect the substrate to the semiconductor chip, wherein the open area includes a first area and a second area disposed in a peripheral part of the first area, and wherein a length of the first area in the first direction is greater than a length of the second area in the first direction.Type: ApplicationFiled: August 2, 2023Publication date: March 14, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Sang Ho Cha, Yun-Rae Cho
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Patent number: 11784137Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.Type: GrantFiled: January 19, 2021Date of Patent: October 10, 2023Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
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Patent number: 11158589Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.Type: GrantFiled: August 6, 2019Date of Patent: October 26, 2021Assignee: Samsung Electronics Co., LtdInventors: Seung Hun Han, Yun Rae Cho, Nam Gyu Baek, Ae Nee Jang
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Publication number: 20210143109Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.Type: ApplicationFiled: January 19, 2021Publication date: May 13, 2021Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
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Patent number: 10950586Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.Type: GrantFiled: June 11, 2019Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yun-Rae Cho
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Patent number: 10930602Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.Type: GrantFiled: July 16, 2019Date of Patent: February 23, 2021Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
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Patent number: 10923407Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.Type: GrantFiled: June 22, 2017Date of Patent: February 16, 2021Inventors: Sundae Kim, Yun-Rae Cho, Namgyu Baek, Seokhyun Lee
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Patent number: 10916509Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.Type: GrantFiled: August 2, 2019Date of Patent: February 9, 2021Inventors: Yun-Rae Cho, Sundae Kim, Hyunggil Baek, Namgyu Baek, Seunghun Shin, Donghoon Won
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Patent number: 10643958Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.Type: GrantFiled: October 12, 2018Date of Patent: May 5, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-dae Kim, Hyung-gil Baek, Yun-rae Cho, Nam-gyu Baek
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Publication number: 20200126930Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.Type: ApplicationFiled: July 16, 2019Publication date: April 23, 2020Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
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Publication number: 20200051932Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: SEUNG HUN HAN, YUN RAE CHO, NAM GYU BAEK, AE NEE JANG
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Patent number: 10559543Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.Type: GrantFiled: June 29, 2018Date of Patent: February 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sundae Kim, Yun-Rae Cho, Namgyu Baek
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Publication number: 20200035649Abstract: A semiconductor package includes a package substrate, a plurality of external connections under the package substrate, a master chip on the package substrate, at least one slave chip on the master chip, a plurality of first bumps and a plurality of second bumps between the package substrate and the master chip, and a plurality of wires connecting the package substrate to the at least one slave chip. The package substrate includes a plurality of first paths connecting the plurality of first bumps to the plurality of external connections and a plurality of second paths connecting the plurality of second bumps to the plurality of wires. An upper surface of the package substrate includes a first edge and a second edge that extend in a first direction and a third edge and a fourth edge that extend in a second direction.Type: ApplicationFiled: April 5, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ae-nee JANG, Nam-gyu BAEK, Yun-rae CHO, Seung-hun HAN
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Patent number: 10490514Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: GrantFiled: April 12, 2019Date of Patent: November 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gyu Baek, Yun-Rae Cho, Hyung-Gil Baek, Sun-Dae Kim
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Publication number: 20190355671Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.Type: ApplicationFiled: August 2, 2019Publication date: November 21, 2019Inventors: Yun-Rae CHO, Sundae KIM, HYUNGGIL BAEK, Namgyu BAEK, Seunghun SHIN, Donghoon WON
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Publication number: 20190295997Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yun-Rae CHO
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Patent number: 10418335Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.Type: GrantFiled: December 21, 2017Date of Patent: September 17, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-Rae Cho, Sundae Kim, Hyunggil Baek, Namgyu Baek, Seunghun Shin, Donghoon Won
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Publication number: 20190237414Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: NAM-GYU BAEK, YUN-RAE CHO, HYUNG-GIL BAEK, SUN-DAE KIM
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Publication number: 20190164915Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.Type: ApplicationFiled: June 29, 2018Publication date: May 30, 2019Inventors: Sundae Kim, Yun-Rae Cho, Namgyu Baek
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Patent number: 10304781Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: GrantFiled: March 15, 2017Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-gyu Baek, Yun-rae Cho, Hyung-gil Baek, Sun-dae Kim