Patents by Inventor Yun Rou Lim

Yun Rou Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955436
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song, Stephen Hall
  • Patent number: 11729900
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Publication number: 20220304143
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 22, 2022
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Patent number: 11277903
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Patent number: 10856407
    Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Yun Rou Lim
  • Publication number: 20200343194
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Inventors: Khang Choong YONG, Ying Ern HO, Yun Rou LIM, Wil Choon SONG, Stephen HALL
  • Publication number: 20200314999
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Publication number: 20200314998
    Abstract: Embodiments herein relate to systems, apparatuses, processes or techniques directed to an impedance cushion coupled with a power plane to provide voltage for a system, where the impedance cushion is dimensioned to suppress resonance of the power plane to mitigate RFI or EMI emanating from the power plane during operation.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Khang Choong YONG, Ying Ern HO, Wil Choon SONG, Yun Rou LIM, Telesphor KAMGAING
  • Patent number: 10734318
    Abstract: A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Yun Rou Lim
  • Patent number: 10484231
    Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Yun Rou Lim
  • Publication number: 20190148269
    Abstract: A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
    Type: Application
    Filed: June 26, 2018
    Publication date: May 16, 2019
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Yun Rou Lim
  • Publication number: 20190008029
    Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Khang Choong Yong, Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Yun Rou Lim
  • Publication number: 20190007259
    Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Khang Choong Yong, Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Yun Rou Lim