Abstract: Disclosed herein is a compound and its use for the prognosis or diagnosis of neurodegenerative diseases. The compound has the structure of formula (I), According to embodiments of the present disclosure, the neurodegenerative disease may be an Alzheimer's disease (AD), Parkinson disease (PD), Huntington's disease (HD), frontotemporal dementia (FTD), Friedreich's ataxia, age-related macular degeneration, or Creutzfeldt-Jakob disease.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.

Abstract: A computing in memory accelerator for applying to a neural network includes a memory, a data buffer unit, a pooling unit, a loss computing unit, a first macro circuit, a second macro unit, a third macro unit, and a multiplexer. The memory is used for saving data. The data buffer unit is coupled to the memory and used to buffer data outputted from the memory. The pooling unit is coupled to the memory and used to pool data for acquiring a maximum pooling value. The loss computing unit is coupled to the memory and used to compute output loss. The first macro circuit, the second macro unit, and the third macro unit are coupled to the data buffer unit. The multiplexer is coupled to the pooling unit, the first macro circuit, the second macro unit, and the third macro unit and used to generate output data.

Abstract: Disclosed herein is a method for identifying and treating an early-stage hepatocellular carcinoma (HCC) in a subject. The method mainly includes determining the level of serum amyloid A (SAA) protein, and providing anti-cancer treatment based on the determined level of SAA protein. According to some embodiments of the present disclosure, the anti-cancer treatment is provided when the determined level of SAA protein is lower than that of a first control sample, or when the determined level of SAA protein is higher than that of a second control sample. In some embodiments, the first control sample is derived from a subject having a late stage HCC, and the second control sample is derived from a subject having a liver disease that is any of hepatitis, liver cirrhosis, or a combination thereof.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.

Abstract: A composition for treating Fabry disease, which includes a polynucleotide having gene editing function for correction of the specific mutation (IVS4+919 G>A) of GLA gene. A method for treating Fabry disease, which uses gene editing systems for correction of the specific mutation (IVS4+919 G>A) of GLA gene in Fabry disease.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

Abstract: Autophagy is the principal catabolic response to nutrient starvation. However, excessive autophagy can be cytotoxic or cytostatic, and contribute to cell death, but its mechanism of induction remains elusive. Here, it was demonstrated that prolonged arginine starvation by ADI-PEG20 induced an autophagy-dependent death of argininosuccinate synthetase 1 (ASS1)-deficient breast cancer cells. Consequently, arginine depleting agents such as ADI-PEG20 may be used in methods for killing one or more argininosuccinate synthetase 1 (ASS1)-deficient breast cancer cells. Further, abundance of ASS1 was either low or absent in more than 60% of 149 random breast cancer biosam pies, which could be exploited as candidates for arginine starvation therapy.

Abstract: Autophagy is the principal catabolic response to nutrient starvation. However, excessive autophagy can be cytotoxic or cytostatic, and contribute to cell death, but its mechanism of induction remains elusive. Here, it was demonstrated that prolonged arginine starvation by ADI-PEG20 induced an autophagy-dependent death of argininosuccinate synthetase 1 (ASS1)-deficient breast cancer cells. Consequently, arginine depleting agents such as ADI-PEG20 may be used in methods for killing one or more argininosuccinate synthetase 1 (ASS1)-deficient breast cancer cells. Further, abundance of ASS1 was either low or absent in more than 60% of 149 random breast cancer biosamples, which could be exploited as candidates for arginine starvation therapy.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.

Abstract: A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.

Abstract: A method including the operations of receiving a preliminary device layout including a plurality of active areas, analyzing the preliminary device layout to identify empty areas between the plurality of active areas, determining the configurations of the active areas bordering the empty areas, selecting a transition cell from a transition cell library in which the transition cell has a transitional configuration for reducing density gradient effects in the active areas adjacent the transition cell, and inserting the transition cells into the empty areas to define a modified device layout.

Abstract: A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell according to a predetermined criterion, wherein the unit cell characterized by the set of parameter values has a circuit characteristic meeting the predetermined criterion; generating a unit cell layout of the unit cell according to the unit cell schematic; generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively; and fabricating the integrated circuit according to the circuit layout.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell according to a predetermined criterion, wherein the unit cell characterized by the set of parameter values has a circuit characteristic meeting the predetermined criterion; generating a unit cell layout of the unit cell according to the unit cell schematic; generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively; and fabricating the integrated circuit according to the circuit layout.