Patents by Inventor Yun-San Huang
Yun-San Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220406921Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: ApplicationFiled: August 22, 2022Publication date: December 22, 2022Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
-
Patent number: 11450756Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: GrantFiled: August 25, 2020Date of Patent: September 20, 2022Assignee: MEDIATEK INC.Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
-
Publication number: 20200388700Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: ApplicationFiled: August 25, 2020Publication date: December 10, 2020Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
-
Patent number: 10790380Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: GrantFiled: September 5, 2018Date of Patent: September 29, 2020Assignee: MEDIATEK INC.Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
-
Publication number: 20190123176Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.Type: ApplicationFiled: September 5, 2018Publication date: April 25, 2019Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
-
Patent number: 9166003Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.Type: GrantFiled: October 25, 2013Date of Patent: October 20, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Meng-Ping Chuang, Yu-Tse Kuo, Chia-Chun Sun, Yun-San Huang
-
Patent number: 8921206Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.Type: GrantFiled: November 30, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
-
Publication number: 20140035111Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.Type: ApplicationFiled: October 25, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Meng-Ping Chuang, Yu-Tse Kuo, Chia-Chun Sun, Yun-San Huang
-
Patent number: 8614463Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.Type: GrantFiled: November 2, 2011Date of Patent: December 24, 2013Assignee: United Microelectronics Corp.Inventors: Meng-Ping Chuang, Yu-Tse Kuo, Chia-Chun Sun, Yun-San Huang
-
Patent number: 8546890Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.Type: GrantFiled: November 27, 2008Date of Patent: October 1, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Li Kuo, Chia-Chun Sun, Chuan-Hsien Fu, Chun-Liang Hou, Yun-San Huang
-
Publication number: 20130137243Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
-
Publication number: 20130105864Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.Type: ApplicationFiled: November 2, 2011Publication date: May 2, 2013Inventors: Meng-Ping Chuang, Yu-Tse Kuo, Chia-Chun Sun, Yun-San Huang
-
Publication number: 20130038336Abstract: A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Jie-Wei SUN, Chao-Hsien Wu, Chia-Chun Sun, Yun-San Huang, Chien-Li Kuo
-
Publication number: 20100127337Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.Type: ApplicationFiled: November 27, 2008Publication date: May 27, 2010Inventors: Chien-Li Kuo, Chia-Chun Sun, Chuan-Hsien Fu, Chun-Liang Hou, Yun-San Huang
-
Patent number: 7588991Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.Type: GrantFiled: July 18, 2007Date of Patent: September 15, 2009Assignee: United Microelectronics Corp.Inventors: Tung-Hsing Lee, Chien-Li Kuo, Yun-San Huang, Chih-Ming Su, Buo-Chin Hsu
-
Publication number: 20090023256Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.Type: ApplicationFiled: July 18, 2007Publication date: January 22, 2009Inventors: Tung-Hsing Lee, Chien-Li Kuo, Yun-San Huang, Chih-Ming Su, Buo-Chin Hsu