Patents by Inventor Yun Seog Lee

Yun Seog Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081833
    Abstract: Disclosed are a method of manufacturing a light-emitting device using mechanical cutting technology and a light-emitting device manufactured through the method, and an embodiment provides a method of implementing a pixelated light-emitting device.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 6, 2025
    Inventors: Byungha SHIN, Joonyun KIM, Jinu PARK, Yun Seog LEE, Young Ho CHU, Kyung Tak YOON, Sunggun YOON, Ki Tae PARK
  • Publication number: 20240381679
    Abstract: A method of manufacturing a perovskite light emitting device using a two-dimensional material capable of implementing the entire visible light region as a light emitting material.
    Type: Application
    Filed: May 10, 2024
    Publication date: November 14, 2024
    Inventors: Byungha Shin, JOONYUN KIM, Jinu Park, Yun Seog Lee, Young Ho Chu, Kijoon Bang, Sunggun Yoon, Ki Tae Park
  • Patent number: 11963372
    Abstract: Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: April 16, 2024
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Yun Seog Lee, Hyunjoon Lee
  • Publication number: 20230266663
    Abstract: A disclosed method of selective separation and transfer of 2D material may include preparing a substrate structure including an adhesion target layer in which at least two different material layers are arranged to be in contact with each other laterally, preparing a crystalline material member including a 2D material, wherein the 2D material constitutes a unit layer, and a plurality of the unit layers form a layered structure through bonding, adhering the crystalline material member to a surface of the adhesion target layer so that a bond is formed between the crystalline material member and the adhesion target layer, and separating the crystalline material member and the adhesion target layer so that a 2D material layer pattern separated from the crystalline material member is formed on the surface of the adhesion target layer.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 24, 2023
    Inventors: Yun Seog Lee, Ki-Tae Park, Sunggun Yoon, Young Ho Chu
  • Publication number: 20230170531
    Abstract: A stacked structure including: a conductive substrate; and a solid electrolyte layer disposed on one surface of the conductive substrate, wherein the solid electrolyte layer includes an inorganic solid electrolyte and the stacked structure has a flexible free-standing film having a thickness of about 5 ?m or less. Provided are an electrochemical battery including the stacked structure, and a method of preparing the stacked structure.
    Type: Application
    Filed: November 22, 2022
    Publication date: June 1, 2023
    Inventors: Sewon Kim, Yun Seog Lee, Mingi Moon, Changhyun Lim
  • Publication number: 20230070983
    Abstract: Disclosed are an anode for a lithium secondary battery including a porous and thin-film anode current collector layer and a method for manufacturing the same.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 9, 2023
    Inventors: Jong Chan Song, Jae Wook Shin, Seong Min Ha, Seung Jong Lee, Won Keun Kim, Kyoung Han Ryu, Yun Seog Lee, Ho Young Kim, Hee Dong Kwak, Jung Taek Kim, Seung Eun Paik, Chang Hyun Lim
  • Patent number: 11588210
    Abstract: Methods of forming a controllable resistive element include forming source and drain regions in a substrate. A battery stack is formed on a substrate between the source and drain regions. Respective anode and cathode electrical connections are formed to the battery stack. Respective source and drain electrical connections are formed.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 21, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Joel P. De Souza, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 11557690
    Abstract: Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
  • Publication number: 20220375994
    Abstract: Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.
    Type: Application
    Filed: September 8, 2021
    Publication date: November 24, 2022
    Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: YUN SEOG LEE, HYUNJOON LEE
  • Patent number: 11444207
    Abstract: A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Babar Khan, Ning Li, Arvind Kumar, Yun Seog Lee, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 11411191
    Abstract: Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
  • Patent number: 11201049
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Ning Li, Qinglong Li, Devendra K. Sadana
  • Patent number: 11201244
    Abstract: Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Babar Khan, Arvind Kumar, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 11133492
    Abstract: A semiconductor structure is provided that contains a non-volatile battery which controls gate bias. The non-volatile battery has a stable voltage and thus the structure may be used in neuromorphic computing. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. In accordance with the present application, the battery stack includes, an anode current collector located on the gate dielectric material, an anode region located on the anode current collector, an ion diffusion barrier material located on the anode region, an electrolyte located on the ion diffusion barrier material, a cathode material located on the electrolyte, and a cathode current collector located on the cathode material.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Joel P. de Souza, Yun Seog Lee, Devendra K. Sadana
  • Patent number: 11106966
    Abstract: A controllable resistive element and methods for controlling the resistance of the same include a resistor layer formed in contact with a shared read/write electrode and a read electrode, the resistor layer having a resistivity that depends on a concentration of charge carrier ions. An electrolyte layer is formed on the resistor layer. A reservoir layer is formed on the electrolyte layer and in contact with a write electrode.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 11081731
    Abstract: High-capacity and high-performance rechargeable batteries containing a cathode material layer having an improved surface roughness is provided. A cathode material layer is provided in which at least an upper portion of the cathode material layer is composed of nanoparticles (i.e., particles having a particle size less than 0.1 ?m). In some embodiments, a lower (or base) portion of the cathode material layer is composed of particles whose particle size is greater than the nanoparticles that form the upper portion of the cathode material layer. In other embodiments, the entirety of the cathode material layer is composed of the nanoparticles. In either embodiment, a conformal layer of a dielectric material can be disposed on a topmost surface of the upper portion of the cathode material layer. The presence of the conformal layer of dielectric material can further improve the smoothness of the cathode material layer.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Devendra K. Sadana, Yun Seog Lee, Joel P. de Souza
  • Patent number: 11023802
    Abstract: Methods for controlling the resistance of a controllable resistive element include determining an amount of electrical resistance change for the controllable resistive element. A concentration difference is determined for a charge carrier ion in a resistor layer of the controllable resistance element that corresponds to the electrical resistance change for the controllable resistive element. A duration and amplitude of a current pulse is determined that changes the charge carrier ion concentration by the determined difference. A positive or negative current pulse is applied to a controllable resistive element for the determined duration.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 10978604
    Abstract: A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Talia S. Gershon, Marinus J. P. Hopstaken, Jeehwan Kim, Yun Seog Lee
  • Patent number: 10950887
    Abstract: A solid-state lithium-based battery is provided in which the formation of lithium islands (i.e., lumps) during a charging/recharging cycle is reduced, or even eliminated. Reduction or elimination of lithium islands (i.e., lumps) can be provided by forming a lithium nucleation enhancement liner between a lithium-based solid-state electrolyte layer and a top electrode of a solid-state lithium based battery.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Yun Seog Lee, Devendra K. Sadana
  • Patent number: 10944128
    Abstract: A solid-state lithium-based battery is provided in which the formation of lithium islands (i.e., lumps) during a charging/recharging cycle is reduced, or even eliminated. Reduction or elimination of lithium islands (i.e., lumps) can be provided by forming a lithium nucleation enhancement liner between a lithium-based solid-state electrolyte layer and a top electrode of a solid-state lithium based battery.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Yun Seog Lee, Devendra K. Sadana