Patents by Inventor YUN SHENG

YUN SHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12350682
    Abstract: A microelectrode device, microfluidic chip, and microfluidic examination method are provided. The microfluidic chip includes a top plate and a microelectrode dot array having several microelectrode devices. Each microelectrode device includes a microfluidic electrode, heating electrode, and control circuit. The control circuit includes a microfluidic control and location sensing circuit, storage circuit, and temperature control circuit. The microfluidic control and location sensing circuit moves a sample within an enabling period of a microfluidic control signal and detects a capacitance value between the microfluidic electrode and the top plate within an enabling period of a location control signal. The storage circuit outputs the capacitance value, reads in the sample operation setup, and reads in the heating control setup within different enabling periods of the clock.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: July 8, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Chen-Yi Lee, Yun-Sheng Chan
  • Publication number: 20250210488
    Abstract: In an embodiment, a device may include a first structure comprising a first surface and a second surface opposite the first surface. The first structure may include a first substrate and a first through substrate via (TSV) exposed from the second surface of the first substrate. The first TSV may have a first width. The device may also include a second TSV exposed from the second surface of the first structure, where the second TSV has a second width smaller than the first width. The device may further include a guard ring surrounding each of the first and second TSVs. Additionally, the device may include a second structure bonded to the first surface of the first structure, where the first surface has first bond pads.
    Type: Application
    Filed: May 6, 2024
    Publication date: June 26, 2025
    Inventors: Chih Hsin Yang, Yun-Sheng Li
  • Patent number: 12340839
    Abstract: A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Hsin-Yuan Yu, Chrong Jung Lin, Ya-Chin King
  • Publication number: 20250157889
    Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.
    Type: Application
    Filed: February 20, 2024
    Publication date: May 15, 2025
    Inventors: Chih-Chieh Chang, Chih Hsin Yang, Mao-Nan Wang, Kuan-Hsun Wang, Yang-Hsin Shih, Yun-Sheng Li, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12300624
    Abstract: The disclosure provides an electronic device which includes a substrate structure, a driving component, and a conductive pattern. The driving component and the conductive pattern are formed on the substrate structure, and the thickness of the conductive pattern is greater than or equal to 0.5 ?m and less than or equal to 15 ?m.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 13, 2025
    Assignee: Innolux Corporation
    Inventors: Jen-Hai Chi, Yun-Sheng Chen, Chia-Chi Ho
  • Patent number: 12283950
    Abstract: The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: April 22, 2025
    Assignee: SUZHOU NOVOSENSE MICROELECTRONICS CO., LTD.
    Inventors: Qihui Chen, Yun Sheng
  • Publication number: 20250118655
    Abstract: A semiconductor structure according to the present disclosure includes a substrate; a through substrate via (TSV) cell over the substrate; and a TSV extending through the TSV cell and the substrate. The TSV cell includes a guard ring structure extending around a perimeter of the TSV cell, and a buffer zone surrounded by the guard ring. The buffer zone includes first dummy transistors, and second dummy transistors. Each of the first dummy transistors includes two first type epitaxial features, a first plurality of nanostructures extending between the two first type epitaxial features, and a first isolation gate structure wrapping over the first plurality of nanostructures. Each of the second dummy transistors includes two second type epitaxial feature, a second plurality of nanostructures extending between the two first type epitaxial features, and a second isolation gate structure wrapping over the second plurality of nanostructures.
    Type: Application
    Filed: January 19, 2024
    Publication date: April 10, 2025
    Inventors: Yun-Sheng Li, Chih Hsin Yang, Chih-Chieh Chang, Mao-Nan Wang, Kuan-Hsun Wang, Yang-Hsin Shih
  • Publication number: 20250089472
    Abstract: An electronic device includes: a substrate, a poly-silicon layer disposed on the substrate, a first metal layer disposed on the substrate, a first insulating layer disposed on the first metal layer, a second insulating layer disposed on the first insulating layer; and a second metal layer covering a part of the second insulating layer and electrically connected to the first metal layer. Wherein a thickness of the second insulating layer under the second metal layer is larger than a thickness of the second insulating layer uncovered with the second metal layer.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Applicant: Red Oak Innovations Limited
    Inventors: Kuang-Pin CHAO, Yun-Sheng CHEN, Ming-Chien SUN
  • Publication number: 20250056889
    Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power line disposed on the substrate, wherein a part of the power line is overlapped with the gate electrode; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve section, and an outline of the gate electrode includes a second curve section.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Yun-Sheng CHEN, Hsia-Ching CHU, Ming-Chien SUN
  • Publication number: 20250038074
    Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: January 30, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12201643
    Abstract: Provided herein are compositions and methods for mechanochemical dynamic therapy.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: January 21, 2025
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: King C. Li, Gun Kim, Qiong Wu, Jeffrey S. Moore, Yun-Sheng Chen
  • Publication number: 20250016033
    Abstract: The present invention relates to a single-channel communication encoding method and decoding method, an encoding circuit, and a decoding circuit. The single-channel communication encoding method comprises: synthesizing a clock signal and a data signal into a long-short code signal, wherein the long-short code signal comprises a long code signal and a short code signal, the pulse width of the long code signal is consistent with that of the clock signal, the pulse width of the short code signal is consistent with that of the clock signal, and the duty ratio of the long code signal and the short code signal is different. According to the present encoding method, the clock signal and the data signal are encoded at the same time, the complexity of the circuit can be reduced, and packaging and wiring of a chip can be reduced.
    Type: Application
    Filed: March 15, 2022
    Publication date: January 9, 2025
    Applicant: SUZHOU NOVOSENSE MICROELECTRONICS CO., LTD.
    Inventors: Jiageng HUANG, Yun SHENG, Jianfeng LIN
  • Publication number: 20240407115
    Abstract: An adapter is disclosed herein. The adapter comprises a base, at least one retention element, a biased latch, a handle, and a switch. The base has a first surface and a second surface opposite the first surface. The first base surface is configured to receive a first surface of a mobile computing device. The at least one retention element is positioned on a front end of the base and is configured to receive a first end of the mobile computing device. The biased latch is positioned on a rear end of the base and is adapted to attach a second end of the mobile computing device. The handle is positioned on the second base surface and the switch is positioned on the second base surface adjacent to the handle. The switch is mechanically linked to the biased latch, and the biased latch is configured to release the mobile computing device from the base when the switch is actuated.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Chieh Kai Wang, Huang Chih Huang, Chi-Ming Wang, Li-Ko Wang, Yun Sheng Chou
  • Publication number: 20240407159
    Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Ya-Chin King, Chrong Lin, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, May-Be Chen, Hsin-Yuan Yu
  • Publication number: 20240405129
    Abstract: An electronic device is provided. The electronic device includes a substrate, a material layer, a first metal layer, and a second metal layer. The material layer is disposed on the substrate, wherein a material of the material layer includes polysilicon, amorphous silicon, or indium gallium zinc oxide. The first metal layer is disposed on the material layer, wherein a first edge of the first metal layer includes a first curved portion. The second metal layer is disposed on the material layer, wherein a second edge of the second metal layer includes a second curved portion, and the second edge surrounds the first edge.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Inventors: Chin-Lung TING, Cheng-Hsu CHOU, Ming-Chun TSENG, Yun-Sheng CHEN, Chih-Hsiung CHANG, Liang-Lu CHEN
  • Patent number: 12159883
    Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: December 3, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yun-Sheng Chen, Hsia-Ching Chu, Ming-Chien Sun
  • Patent number: 12156436
    Abstract: An electronic device includes: a substrate, a poly-silicon layer disposed on the substrate, a first metal layer disposed on the substrate, a first insulating layer disposed on the first metal layer, a second insulating layer disposed on the first insulating layer; and a second metal layer covering a part of the second insulating layer and electrically connected to the first metal layer. Wherein a thickness of the second insulating layer under the second metal layer is larger than a thickness of the second insulating layer uncovered with the second metal layer.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: November 26, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kuang-Pin Chao, Yun-Sheng Chen, Ming-Chien Sun
  • Publication number: 20240355388
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-Chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
  • Publication number: 20240345129
    Abstract: Decoupled optical force nanoscopy allows for measurements of optical forces with nanoscale spatial and temporal resolution. A sample is illuminated with temporally modulated laser light. Optical force data are measured by scanning a cantilever (e.g., of a scanning probe microscope) over the sample to measure optical forces generated by illuminating the sample with the temporally modulated laser light. The optical force data are analyzed in the frequency domain to separate the optical force data into different components, such as photothermal force components, optical gradient force components, photoacoustic force components, and the like.
    Type: Application
    Filed: April 12, 2024
    Publication date: October 17, 2024
    Inventors: Yang Zhao, Yun-Sheng Chen, Hanwei Wang
  • Publication number: 20240324474
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der CHIH, Wen-Zhang LIN, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Chrong-Jung LIN, Ya-Chin KING, Cheng-Jun LIN, Wang-Yi LEE