Patents by Inventor Yun-sheng Chen

Yun-sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056889
    Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power line disposed on the substrate, wherein a part of the power line is overlapped with the gate electrode; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve section, and an outline of the gate electrode includes a second curve section.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Yun-Sheng CHEN, Hsia-Ching CHU, Ming-Chien SUN
  • Publication number: 20250038074
    Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: January 30, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250027227
    Abstract: Provided are a silicon carbide crystal growth device and a quality control method. The device includes: an annealing unit, a crystal growth unit, an atmosphere control unit, and a transport system; the atmosphere control unit provides a gas environment with low water, oxygen and nitrogen; the transport system transports a plurality of target objects after high-temperature purification by the annealing unit to the atmosphere control unit; after assembling silicon carbide seed crystal and silicon carbide powder in a graphite crucible and covering with thermal insulation material to form a container inside the atmosphere control unit, the transport system transports the container to the crystal growth unit. The method uses a weighing system in a chamber of the crystal growth unit to detect a weight change of silicon carbide seed crystal and silicon carbide powder during a crystal growth process through a plurality of weight sensors of the weighing system.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Yun-Fu Chen, Wei-Tse Hsu, Min-Sheng Chu, Chien-Li Yang, Tsu-Hsiang Lin, Yuan-Hong Huang
  • Patent number: 12201643
    Abstract: Provided herein are compositions and methods for mechanochemical dynamic therapy.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: January 21, 2025
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: King C. Li, Gun Kim, Qiong Wu, Jeffrey S. Moore, Yun-Sheng Chen
  • Publication number: 20240405129
    Abstract: An electronic device is provided. The electronic device includes a substrate, a material layer, a first metal layer, and a second metal layer. The material layer is disposed on the substrate, wherein a material of the material layer includes polysilicon, amorphous silicon, or indium gallium zinc oxide. The first metal layer is disposed on the material layer, wherein a first edge of the first metal layer includes a first curved portion. The second metal layer is disposed on the material layer, wherein a second edge of the second metal layer includes a second curved portion, and the second edge surrounds the first edge.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Inventors: Chin-Lung TING, Cheng-Hsu CHOU, Ming-Chun TSENG, Yun-Sheng CHEN, Chih-Hsiung CHANG, Liang-Lu CHEN
  • Publication number: 20240407159
    Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Ya-Chin King, Chrong Lin, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, May-Be Chen, Hsin-Yuan Yu
  • Patent number: 12159883
    Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: December 3, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yun-Sheng Chen, Hsia-Ching Chu, Ming-Chien Sun
  • Patent number: 12156436
    Abstract: An electronic device includes: a substrate, a poly-silicon layer disposed on the substrate, a first metal layer disposed on the substrate, a first insulating layer disposed on the first metal layer, a second insulating layer disposed on the first insulating layer; and a second metal layer covering a part of the second insulating layer and electrically connected to the first metal layer. Wherein a thickness of the second insulating layer under the second metal layer is larger than a thickness of the second insulating layer uncovered with the second metal layer.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: November 26, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kuang-Pin Chao, Yun-Sheng Chen, Ming-Chien Sun
  • Publication number: 20240355388
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-Chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
  • Publication number: 20240345129
    Abstract: Decoupled optical force nanoscopy allows for measurements of optical forces with nanoscale spatial and temporal resolution. A sample is illuminated with temporally modulated laser light. Optical force data are measured by scanning a cantilever (e.g., of a scanning probe microscope) over the sample to measure optical forces generated by illuminating the sample with the temporally modulated laser light. The optical force data are analyzed in the frequency domain to separate the optical force data into different components, such as photothermal force components, optical gradient force components, photoacoustic force components, and the like.
    Type: Application
    Filed: April 12, 2024
    Publication date: October 17, 2024
    Inventors: Yang Zhao, Yun-Sheng Chen, Hanwei Wang
  • Publication number: 20240324474
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der CHIH, Wen-Zhang LIN, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Chrong-Jung LIN, Ya-Chin KING, Cheng-Jun LIN, Wang-Yi LEE
  • Patent number: 12094983
    Abstract: A display device is provided. The display device includes a substrate, a channel layer, a first metal layer, and a second metal layer. The channel layer is disposed on the substrate and includes a first channel layer and a second channel layer. The first metal layer is disposed on the channel layer and includes a first gate and a second gate. The second metal layer is disposed over the first metal layer and includes a first source, a first drain, and a second source. The first gate, the first source, the first drain, and the first channel layer form a first transistor. The second gate, the second source, the first drain, and the second channel layer form a second transistor. The first transistor and the second transistor are connected in parallel.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: September 17, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Lung Ting, Cheng-Hsu Chou, Ming-Chun Tseng, Yun-Sheng Chen, Chih-Hsiung Chang, Liang-Lu Chen
  • Patent number: 12051466
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-chin King, Wen Zhang Lin, Chrong Jung Lin, Hsin-Yuan Yu
  • Patent number: 12041860
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Wen-Zhang Lin, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Chrong-Jung Lin, Ya-Chin King, Cheng-Jun Lin, Wang-Yi Lee
  • Patent number: 11943936
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Der Chih, May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen Zhang Lin, Chrong Jung Lin, Ya-Chin King, Chieh Lee, Wang-Yi Lee
  • Publication number: 20240014224
    Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 11, 2024
    Inventors: Yun-Sheng CHEN, Hsia-Ching CHU, Ming-Chien SUN
  • Publication number: 20230326521
    Abstract: A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der CHIH, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Hsin-Yuan YU, Chrong Jung LIN, Ya-Chin KING
  • Patent number: 11733326
    Abstract: A reconfigurable metamaterial is used to enhance the reception field of a radio frequency (“RF”) coil for use in magnetic resonance imaging (“MRI”). In general, the metamaterial can be a metasurface, which may be flexible, having a periodic array of resonators. Each resonator in the periodic array can be defined as a unit cell of the metamaterial and/or metasurface. The unit cells include a first conductor and a second conductor separated by an insulator layer. The first conductor can be a solid conductor and the second conductor can be a conductive fluid (e.g., a liquid metal, a liquid metal alloy) contained within a microfluidic channel. Varying the volume of conductive fluid in each unit cell adjust the signal enhancement ratio of the metamaterial.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 22, 2023
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Yang Zhao, Yun-Sheng Chen, Hanwei Wang
  • Patent number: 11735602
    Abstract: The disclosed display device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; and a connecting member disposed on the substrate and electrically connecting to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, and a minimum width of the second part in a direction perpendicular to the extension direction is less than a maximum width of the first part in the direction.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: August 22, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Yun-Sheng Chen, Hsia-Ching Chu, Ming-Chien Sun
  • Publication number: 20230255065
    Abstract: An electronic device includes: a substrate, a poly-silicon layer disposed on the substrate, a first metal layer disposed on the substrate, a first insulating layer disposed on the first metal layer, a second insulating layer disposed on the first insulating layer; and a second metal layer covering a part of the second insulating layer and electrically connected to the first metal layer. Wherein a thickness of the second insulating layer under the second metal layer is larger than a thickness of the second insulating layer uncovered with the second metal layer.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Inventors: Kuang-Pin CHAO, Yun-Sheng CHEN, Ming-Chien SUN