Abstract: A display substrate and a display apparatus are provided, and the display substrate includes a pixel circuit with a light emitting module configured to emit light; a driving module configured to drive the light emitting module to emit light based on a driving voltage in a luminescence stage; a storage module configured to maintain and provide the driving voltage to the driving module in the luminescence stage; a first transistor, having a first electrode coupled to a position from which the driving module acquires the driving voltage; a second transistor, having a first electrode coupled to the first electrode of the first transistor, and a second electrode being not directly coupled to a signal source; and a voltage stabilizing capacitor, having a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to a constant voltage signal source.

Abstract: An interaction method and apparatus and an electronic device. The method comprises: displaying a first application interface, wherein the first application interface comprises an interface of a first application; and creating a second application account in the first application interface, wherein the second application account is used for logging in a second application. Therefore, a new interaction mode is provided.

Abstract: The present invention discloses a method for removing carbon dioxide from a reaction gas. The present invention fully utilizes the available heat in each part of the carbon dioxide removal system to reduce external heat exchange, and thereby significantly reduces the carbon dioxide content in the gas returned to the reactor, and also greatly reduces the steam consumption during the regeneration of the rich decarburizing solution. The present invention also discloses a system for removing carbon dioxide from the reaction gas and use thereof.

Abstract: A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.

Abstract: Provided is a pixel circuit. In the pixel circuit, a data write circuit may transmit a data signal to a first node; a compensation circuit may adjust a potential of a second node and a potential of a third node based on a gate drive signal; a first reset circuit may transmit a first initial power supply signal to the third node; a drive circuit may transmit a drive signal to the second node based on the potential of the third node and a potential of the first node; and a second reset circuit may transmit a second initial power supply signal to a first electrode of a light-emitting element.

Abstract: Displays and display driving methods implement a pixel set/reset scheme. Pixel cells of an example display each include a set terminal, a reset terminal, an output terminal, and a set/reset circuit. Responsive to receiving a set signal on the set terminal, the set/reset circuit asserts a first signal on the output terminal and maintains the first signal on the output terminal until a reset signal is received on the reset terminal. Responsive to receiving a reset signal on the reset terminal, the set/reset circuit asserts a second signal on the output terminal and maintains the second signal on the output terminal until a set signal is received on the set terminal. The optical output of the pixel depends on when the first signal and the second signal are asserted on the output terminal of the set/reset circuit during a predefined modulation period.

Abstract: Displays and display driving methods implement a pixel set/reset scheme. Pixel cells of an example display each include a set terminal, a reset terminal, an output terminal, and a set/reset circuit. Responsive to receiving a set signal on the set terminal, the set/reset circuit asserts a first signal on the output terminal and maintains the first signal on the output terminal until a reset signal is received on the reset terminal. Responsive to receiving a reset signal on the reset terminal, the set/reset circuit asserts a second signal on the output terminal and maintains the second signal on the output terminal until a set signal is received on the set terminal. The optical output of the pixel depends on when the first signal and the second signal are asserted on the output terminal of the set/reset circuit during a predefined modulation period.

Abstract: The present invention discloses a sunshade umbrella capable of adjusting umbrella surface angle, including an upright rod and an upright rod handle which moves up and down along the upright rod, wherein one end of the upright rod is connected with umbrella base, the other end of the upright rod is hinged with the connecting rod, the other end of the connecting rod is hinged with a circumferential fixed hanger rod, the hanger rod is hinged with the upright rod handle, an umbrella surface angle adjusting device is mounted on one end of the hanger rod, an executing device that takes the circumferential movement around the hanger rod is mounted on the other end of the hanger rod, and the executing device is connected with an upper umbrella plate. This umbrella has the following advantages: increased overall firmness of the sunshade umbrella, simple structure, and is convenient to operate.

Abstract: The present invention discloses a sunshade umbrella capable of adjusting umbrella surface angle, including an upright rod and an upright rod handle which moves up and down along the upright rod, wherein one end of the upright rod is connected with umbrella base, the other end of the upright rod is hinged with the connecting rod, the other end of the connecting rod is hinged with a circumferential fixed hanger rod, the hanger rod is hinged with the upright rod handle, an umbrella surface angle adjusting device is mounted on one end of the hanger rod, an executing device that takes the circumferential movement around the hanger rod is mounted on the other end of the hanger rod, and the executing device is connected with an upper umbrella plate. This umbrella has the following advantages: increased overall firmness of the sunshade umbrella, simple structure, and is convenient to operate.

Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.

Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.

Abstract: A novel method and circuit are disclosed for providing an alternate function to a semiconductor device having a normal operating voltage range and an input pin for receiving an input signal of a voltage level within a normal signal voltage range, for selecting an alternate function, whose steps consist of determining, when a voltage is received at the input pin, whether the voltage is within a normal signal voltage range, enabling the performing of a primary function if the signal voltage is within a normal signal voltage range, and initiating an alternate function when the voltage is outside of the normal signal voltage range.

Abstract: The invention concerns a cooling and molding water tank for a plastic complicated profile. A plurality of molding blocks and water collection plates are provided along the length inside the tank, and they are spaced each other. The advantage of this invention is that: the cooling water flows alternately in cycle or periphery-inner-periphery. It makes the complicated profile cool homogeneously and efficiently upon the high speed extrusion pulling and provides the profile with good molding effect and quality.

Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.

Abstract: The invention concerns a cooling and molding water tank for a plastic complicated profile. The tank comprises a tank body including a front end block, a rear end block, a top cover, two side plates, bottom plate and a plurality of foot plates, which are in bolted or hinged joint. A water inlet pipe is provided near the front end of the side plate, a water outlet pipe is provided near the rear end. A vacuum valve and a vacuum gauge are provided on the top cover. A plurality of molding blocks and water collection plates are provided along the length inside the tank, and they are spaced each other. The distribution of their arrangement is closer to disperser from the front to the end. The advantage of this invention is that: the cooling water flows alternately in cycle of periphery-inner-periphery. It makes the complicated profile cool homogeneously and efficiently upon the high speed extrusion pulling and provides the profile with good molding effect and quality.

Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.