Abstract: A method and apparatus for determining the status of frame data transmission from an imaging device. According to one aspect of the invention, a graphics controller interfaces with a host and an imaging device, preferably a camera. A count value is specified, preferably by the host. Frame data received from the imaging device are counted to determine an actual count. A comparison is made between the actual count and the count value. Preferably, responsive to the comparison, an indication signal is generated for interrupting the host.

Abstract: Data throughput of the serial host interface is improved by combining command and register address data into a single index word to be transmitted through the serial host interface. The least significant bit (LSB) of the index word specifies the command and the remainder of the index word specifies the register address. Thus, transmission of just two words is required to transmit each of a single write data word and a single read data word. Additionally, the serial host interface provides for elimination of the dummy access word as required when performing a read transmission using a conventional serial host interface protocol.

Abstract: A graphics controller for animating a tiled background is described. The graphics controller includes a host interface for communicating with an external host CPU and a plurality of registers in communication with the host interface. Logic circuitry is configured to select between tile image data and main image data when passing pixel values to a display controller. The logic responds to values stored in the registers to for positioning the main image within the display. A method carried out by the graphics controller and a method for using the graphics controller are also described.

Abstract: A size limiter module used to limit a file size of an encoded file is disclosed. The size limiter module includes a size limiter set-up calculator and a size limiter processing engine. The size limiter calculator is configured to identify a maximum bit size for a set of data to be encoded based on a maximum value for the file size of the encoded file. The size limiter processing engine is configured to be in communication with the size limiter set-up calculator to process the set of data to be encoded and to monitor a cumulative bit size for the set of data according to an order. When the cumulative bit size is greater than a maximum bit size, the size limiter processing engine inserts end of block data into the set of data. The end of block data signals the substitution of a null value for all data units subsequent to the end of block data.

Abstract: A graphics controller includes a memory region configured to store image data for display on a display panel in communication with the graphics controller. Interface circuitry modules where each of the interface circuitry modules is configured to transmit data from the graphics controller over a set of shared data lines are provided. Selection circuitry configured to select data from one of the interface circuitry modules for transmission over the set of shared data lines is included. Line sharing circuitry configured to inform each of the interface circuitry modules to transmit control data is included. The line sharing circuitry is further configured to generate select signals for the selection circuitry. The select signals enable the selection circuitry to select the data from one of the interface circuitry modules for transmission over the shared data lines. A method for driving a display panel and peripheral devices associated with the display panel through common data lines is also provided.

Abstract: A graphics controller includes circuitry for updating multiple display panels over a shared set of data lines associated with the multiple display panels. The circuitry for updating multiple display panels includes circuitry for generating control signals over control lines dedicated to each of the multiple display panels. A memory region configured to store image data for display on the multiple display panels is included with the circuitry for updating multiple display panels. Circuitry configured to select image data associated with one of the multiple display panels for display during an inactive period associated with an other one of the multiple display panels is provided with the circuitry for updating multiple display panels. A method for displaying image data on an RGB panel and a parallel panel simultaneously is also provided.

Abstract: An indirect interface of the present invention is for use between a processing device and a display device, the indirect interface using fewer pins by following a set of predetermined rules. Address and data signals are multiplexed onto an address/data bus of the indirect interface so that a single set of pins can be used as both address line/pins and data line/pins. In one preferred embodiment, a processor interface means transfers signals between the indirect interface system and the external processing device and a display interface means transfers signals between the indirect interface system and the external display device. In one preferred embodiment, the signals may be transferred between the indirect interface system and the external processing device using a command cycle followed by at least one data cycle.