Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

Abstract: A pixel voltage compensation method, a pixel voltage compensator device and a display device are provided. The compensation method includes: determining a capacitance between at least one data line adjacent to a target pixel electrode and the target pixel electrode; detecting a voltage difference between a driving voltage of the data line and a driving voltage of the target pixel electrode in a period from a start of present charging of the target pixel electrode to a start of next charging; calculating a variation of the driving voltage of the target pixel electrode caused by the capacitance and the voltage difference; and compensating for the driving voltage of the target pixel electrode according to the variation. This compensation method can suppress the phenomenon of voltage cross-talk, and thus can improve the display effect of the display device.

Abstract: A phase shifter, a phase shift degree compensation device, and a phase shift degree compensation method are provided. The phase shifter includes a first substrate and a second substrate that are oppositely arranged, a resonant circuit, a signal line, and a first alignment layer are on a side of the first substrate facing the second substrate, a conductive layer and a second alignment layer are on a side of the second substrate facing the first substrate, a liquid crystal layer is between the first alignment layer and the second alignment layer, and the resonant circuit is configured to detect an actual equivalent dielectric constant of the liquid crystal layer.

Abstract: An array substrate and a display panel are provided. The array substrate includes: a plurality of sub-pixels arranged along a row direction and a column direction, four or six adjacent sub-pixel columns constituting a sub-pixel column group; a plurality of data lines extending along the column direction and comprising a first data line and a second data line. In the row direction, the first data line and the second data line are respectively provided on two sides of the sub-pixel column group, and a data line pair including the first data line and the second data line is located between adjacent sub-pixel column groups.

Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

Abstract: A pixel voltage compensation method, a pixel voltage compensator device and a display device are provided. The compensation method includes: determining a capacitance between at least one data line adjacent to a target pixel electrode and the target pixel electrode; detecting a voltage difference between a driving voltage of the data line and a driving voltage of the target pixel electrode in a period from a start of present charging of the target pixel electrode to a start of next charging; calculating a variation of the driving voltage of the target pixel electrode caused by the capacitance and the voltage difference; and compensating for the driving voltage of the target pixel electrode according to the variation. This compensation method can suppress the phenomenon of voltage cross-talk, and thus can improve the display effect of the display device.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.

Abstract: A phase shifter, a phase shift degree compensation device, and a phase shift degree compensation method are provided.

Abstract: An array substrate and a display panel are provided. The array substrate includes: a plurality of sub-pixels arranged along a row direction and a column direction, four or six adjacent sub-pixel columns constituting a sub-pixel column group; a plurality of data lines extending along the column direction and comprising a first data line and a second data line. In the row direction, the first data line and the second data line are respectively provided on two sides of the sub-pixel column group, and a data line pair including the first data line and the second data line is located between adjacent sub-pixel column groups.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.

Abstract: An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.

Abstract: A method for preparing a liquid crystal alignment layer, a liquid crystal alignment layer, and a display device. The method for preparing a liquid crystal alignment layer includes: S1, dripping liquid crystals and performing cell-assembling, wherein a liquid alignment material is added to the liquid crystals and the alignment material is curable and includes molecules capable of inducing alignment of liquid crystal molecules; S2, applying an electric field or a magnetic field, wherein the direction of the electric field is approximately the same as a preset direction of the liquid crystal alignment layer, and the direction of the magnetic field is perpendicular to the preset direction of the liquid crystal alignment layer; and S3, performing curing while maintaining the electric field or the magnetic field until the alignment material completes the curing reaction.

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a plurality of shift register units, a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. The plurality of gate lines crossing the plurality of data lines defines a plurality of pixel regions. Each of the pixel regions is divided into a driving zone and a pixel unit zone. A plurality of the driving zones in a same column constitute at least one unit region and each of the shift register units is disposed in one of the unit regions to provide scanning signals to the gate line connected thereto.

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Abstract: A display driving method, a display panel and a display device. In the display driving method, the voltage (Vgl) of a gate turning-off signal at least changes once during the period of applying the gate turning-off signal to each gate line (Gate 1, Gate 2, . . . ). A pixel voltage signal is varied as the gate turning-off signal changes. Thus, the variation frequency of the pixel voltage signal within the display time of each frame is increased by changing the gate turning-off signal within the display time of each frame, which is equivalent to increase the refreshing frequency, so that the human eyes cannot recognize flicker.

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.