Patents by Inventor YUN SIK IM

YUN SIK IM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210341780
    Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.
    Type: Application
    Filed: September 6, 2018
    Publication date: November 4, 2021
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Xue Dong, Liwei Liu, Xinxing Wang, Yun Sik Im, Hyun Sic Choi, Jaegeon You, Yinglong Huang, Heecheol Kim
  • Publication number: 20210287622
    Abstract: A pixel voltage compensation method, a pixel voltage compensator device and a display device are provided. The compensation method includes: determining a capacitance between at least one data line adjacent to a target pixel electrode and the target pixel electrode; detecting a voltage difference between a driving voltage of the data line and a driving voltage of the target pixel electrode in a period from a start of present charging of the target pixel electrode to a start of next charging; calculating a variation of the driving voltage of the target pixel electrode caused by the capacitance and the voltage difference; and compensating for the driving voltage of the target pixel electrode according to the variation. This compensation method can suppress the phenomenon of voltage cross-talk, and thus can improve the display effect of the display device.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 16, 2021
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liwei LIU, Yun Sik IM, Yoon Sung UM
  • Patent number: 11073731
    Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 27, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yoon Sung Um, Shunhang Zhang, Yun Sik Im
  • Publication number: 20210210827
    Abstract: A phase shifter, a phase shift degree compensation device, and a phase shift degree compensation method are provided.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 8, 2021
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongrun WANG, Kai HOU, Liwei LIU, Feng LIAO, Shunhang ZHANG, Hui ZHANG, Yu'e JIA, Yun Sik IM
  • Publication number: 20210149260
    Abstract: An array substrate and a display panel are provided. The array substrate includes: a plurality of sub-pixels arranged along a row direction and a column direction, four or six adjacent sub-pixel columns constituting a sub-pixel column group; a plurality of data lines extending along the column direction and comprising a first data line and a second data line. In the row direction, the first data line and the second data line are respectively provided on two sides of the sub-pixel column group, and a data line pair including the first data line and the second data line is located between adjacent sub-pixel column groups.
    Type: Application
    Filed: June 26, 2019
    Publication date: May 20, 2021
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yoon Sung UM, Yu'e JIA, Feng LIAO, Hui ZHANG, Shunhang ZHANG, Hongrun WANG, Liwei LIU, Kai HOU, Yun Sik IM
  • Publication number: 20200272005
    Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.
    Type: Application
    Filed: November 2, 2017
    Publication date: August 27, 2020
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yoon Sung UM, Shunhang ZHANG, Yun Sik IM
  • Patent number: 10679565
    Abstract: An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 9, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiha Kim, Seung Woo Han, Guangliang Shang, Haoliang Zheng, Xing Yao, Mingfu Han, Zhichong Wang, Lijun Yuan, Yun Sik Im, Yinglong Huang, Xue Dong
  • Patent number: 10629151
    Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiha Kim, Lijun Yuan, Zhichong Wang, Mingfu Han, Xing Yao, Guangliang Shang, Seung Woo Han, Yun Sik Im, Jing Lv, Yinglong Huang, Jung Mok Jun, Haoliang Zheng
  • Patent number: 10613391
    Abstract: A method for preparing a liquid crystal alignment layer, a liquid crystal alignment layer, and a display device. The method for preparing a liquid crystal alignment layer includes: S1, dripping liquid crystals and performing cell-assembling, wherein a liquid alignment material is added to the liquid crystals and the alignment material is curable and includes molecules capable of inducing alignment of liquid crystal molecules; S2, applying an electric field or a magnetic field, wherein the direction of the electric field is approximately the same as a preset direction of the liquid crystal alignment layer, and the direction of the magnetic field is perpendicular to the preset direction of the liquid crystal alignment layer; and S3, performing curing while maintaining the electric field or the magnetic field until the alignment material completes the curing reaction.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qiangtao Wang, Yun Sik Im
  • Patent number: 10540938
    Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: January 21, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jiha Kim, Seung Woo Han, Guangliang Shang, Xing Yao, Haoliang Zheng, Mingfu Han, Zhichong Wang, Lijun Yuan, Yun Sik Im, Jing Lv, Yinglong Huang, Xue Dong
  • Patent number: 10504602
    Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a plurality of shift register units, a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. The plurality of gate lines crossing the plurality of data lines defines a plurality of pixel regions. Each of the pixel regions is divided into a driving zone and a pixel unit zone. A plurality of the driving zones in a same column constitute at least one unit region and each of the shift register units is disposed in one of the unit regions to provide scanning signals to the gate line connected thereto.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: December 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xing Yao, Seung-Woo Han, Guangliang Shang, Mingfu Han, Haoliang Zheng, Yun-Sik Im
  • Patent number: 10504469
    Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 10, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jiha Kim, Seung Woo Han, Guangliang Shang, Xing Yao, Haoliang Zheng, Mingfu Han, Zhichong Wang, Lijun Yuan, Yun Sik Im, Jing Lv, Yinglong Huang, Xue Dong
  • Patent number: 10453411
    Abstract: A display driving method, a display panel and a display device. In the display driving method, the voltage (Vgl) of a gate turning-off signal at least changes once during the period of applying the gate turning-off signal to each gate line (Gate 1, Gate 2, . . . ). A pixel voltage signal is varied as the gate turning-off signal changes. Thus, the variation frequency of the pixel voltage signal within the display time of each frame is increased by changing the gate turning-off signal within the display time of each frame, which is equivalent to increase the refreshing frequency, so that the human eyes cannot recognize flicker.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 22, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yoon Sung Um, Yu'e Jia, Kuanjun Peng, Yun Sik Im
  • Publication number: 20190279588
    Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.
    Type: Application
    Filed: December 14, 2017
    Publication date: September 12, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiha KIM, Lijun YUAN, Zhichong WANG, Mingfu HAN, Xing YAO, Guangliang SHANG, Seung Woo HAN, Yun Sik IM, Jing LV, Yinglong HUANG, Jung Mok JUN, Haoliang ZHENG
  • Publication number: 20190279574
    Abstract: An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.
    Type: Application
    Filed: November 7, 2017
    Publication date: September 12, 2019
    Applicant: BOB TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiha KIM, Seung Woo HAN, Guangliang SHANG, Haoliang ZHENG, Xing YAO, Mingfu HAN, Zhichong WANG, Lijun YUAN, Yun Sik IM, Yinglong HUANG, Xue DONG
  • Patent number: 10367008
    Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a base substrate, and, subpixels disposed on the base substrate. A first electrode and a second electrode are disposed in each of the subpixels; the first electrode includes first electrode strips; the second electrode includes second electrode strips. A distance between a projection of one second electrode strip and a projection of a first electrode strip adjacent to the second electrode strip in the first direction is S1; a distance between the projection of the second electrode strip and a projection of one first electrode strip adjacent to the second electrode strip in a direction opposite to the first direction is S2; a first domain includes a part in which S1 is greater than S2; and a second domain includes a part in which S1 is less than S2.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 30, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hui Li, Yun Sik Im, Hyun Sic Choi, Kuanjun Peng, Yu'e Jia, Hui Zhang
  • Patent number: 10339885
    Abstract: An array substrate, a display device and a driving method thereof are provided. The array substrate includes a base substrate, a driver provided on the base substrate, a plurality of gate lines and a plurality of gate line overlap parts, each of the gate line overlap parts has a portion which overlaps a corresponding gate line of the gate lines in a direction perpendicular to the base substrate; the driver is connected with the plurality of the gate line overlap parts and is configured to, at one or both of a time when a potential of the gate line is changed from a turn-on potential to a turn-off potential and a time from the turn-off potential to the turn-on potential, make the gate line overlap part in a floating state, or make the potential of the gate line overlap part equal to the changed potential.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yoon Sung Um, Yun Sik Im
  • Patent number: 10330984
    Abstract: An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises a lining substrate and an electrode pattern formed on the lining substrate, and the electrode pattern includes a plurality of strip-shaped electrodes. There are a plurality of strip-shaped protrusions on an upper surface of the lining substrate, and at least part of strip-shaped electrodes among the plurality of strip-shaped electrodes are formed on the strip-shaped protrusions one-to-one; and there is an included angle between an extending direction of the strip-shaped electrodes and an extending direction of the strip-shaped protrusions, and the included angle is configured so that a rubbing direction of an alignment film is along the extending direction of the strip-shaped protrusions.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 25, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yoon Sung Um, Yun Sik Im, Hyun Sic Choi, Hui Li, Jung Mok Jun
  • Patent number: 10235919
    Abstract: A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: March 19, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangliang Shang, Xing Yao, Mingfu Han, Seung-Woo Han, Yun-Sik Im, Jing Lv, Yinglong Huang, Jung-Mok Jun, Xue Dong, Haoliang Zheng, Lijun Yuan, Zhichong Wang, Ji Ha Kim
  • Publication number: 20190057638
    Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 21, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiha KIM, Seung Woo HAN, Guangliang SHANG, Xing YAO, Haoliang ZHENG, Mingfu HAN, Zhichong WANG, Lijun YUAN, Yun Sik IM, Jing LV, Yinglong HUANG, Xue DONG