Abstract: A semiconductor device includes a first semiconductor structure including circuit devices on a first substrate, a lower interconnection structure connected to the circuit devices, and a lower bonding structure connected to the lower interconnection structure; and a second semiconductor structure including a second substrate on the first semiconductor structure, a stopper layer in contact with a lower surface of the second substrate, gate electrodes stacked and spaced apart from each other in a vertical direction, channel structures penetrating through the gate electrodes, and each including a channel layer, an upper interconnection structure below the gate electrodes, a peripheral contact plug spaced apart from the second substrate, and an upper bonding structure bonded to the lower bonding structure, wherein the channel structures penetrate at least a portion of the stopper layer, and wherein the peripheral contact plug penetrates at least a portion of the stopper layer.

Abstract: A semiconductor memory device includes: a stack including interlayer insulating layers and conductive patterns, which are alternately stacked; a source conductive pattern on the stack; and vertical structures provided to penetrate the stack and connected to the source conductive pattern. Each of the vertical structures includes: a vertical channel pattern; a data storage pattern enclosing an outer side surface of the vertical channel pattern; a vertical insulating pillar in the vertical channel pattern; and a vertical conductive pillar disposed between the vertical insulating pillar and the source conductive pattern to connect the vertical channel pattern to the source conductive pattern.

Abstract: A three-dimensional semiconductor memory device is provided. The memory device includes a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure and including a cell array region and a cell array contact region. The cell array structure includes a stack structure including alternately stacked interlayer insulating layers and gate electrodes, a first source conductive pattern, a second source conductive pattern, and a third source conductive pattern sequentially stacked on the stack structure. The first to third source conductive patterns include different materials from each other. Vertical channel structures extending into a lower portion of the first source conductive pattern through the stack structure is included. The first to third source conductive patterns extend from the cell array region to the cell array contact region.

Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems. The three-dimensional semiconductor memory device includes a first substrate that includes a cell array region and a contact region, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure wherein the cell array structure includes interlayer dielectric layers and gate electrodes that are alternately stacked, a dielectric layer on the stack structure, and a second substrate on the stack structure, a mold structure that penetrates the stack structure and includes a dielectric material, and a first through structure and a second through structure that penetrate the mold structure and are spaced apart from each other.

Abstract: A semiconductor device includes a first semiconductor structure including a lower bonding structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, an upper bonding structure bonded to the lower bonding structure, a plate conductive layer disposed on an upper surface of the second substrate, electrically connected to a channel layer, and including a metal material, and an isolation structure penetrating an entirety of the gate electrodes and extending in a second direction perpendicular to the first direction. The isolation structure includes a vertical conductive layer that extends from and is integrated with the plate conductive layer, and that includes a same metal material as the metal material of the plate conductive layer.

Abstract: A three-dimensional semiconductor memory device includes a substrate, a peripheral circuit structure provided on the substrate, and a cell array structure provided on the peripheral circuit structure. The cell array structure includes a stack including alternating interlayer insulating layers and conductive patterns, the conductive patterns including gate electrodes and a first source conductive pattern that is an uppermost pattern of the conductive patterns, a second source conductive pattern provided on the stack and in contact with a top surface of the first source conductive pattern, the second source conductive pattern including a material different from a material of the first source conductive pattern, and vertical channel structures provided to penetrate the stack and to be inserted into a lower portion of the second source conductive pattern. The vertical channel structures include vertical semiconductor patterns connected to the second source conductive pattern.

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure directly on the first substrate structure. The second substrate structure includes a plate layer comprising a conductive material, gate electrodes stacked below the plate layer, channel structures passing through the gate electrodes and each including a channel layer, separation regions penetrating through the gate electrodes and extending in first and second directions and source contacts in the plate layer and disposed on the separation regions. The source contacts extend in the second direction. Second bonding metal layers are connected to the first bonding metal layers. The plate layer is in direct contact with lateral side surfaces of the source contacts and an upper end of the channel layer of each of the channel structures, and is electrically connected to the source contacts and the channel layer.

Abstract: A semiconductor device includes first and second substrates including cell and peripheral circuit regions, first and second gate electrode structures, first and second channels, and first to third transistors. The first and second gate electrode structures include first and second gate electrodes in a vertical direction. The first and second channel extend through the first and second gate electrode structures. The first transistor is on the peripheral circuit region. The second gate electrode structure is on the first gate electrode structure and the first transistor. The second and third transistors are on the second gate electrode structure. The second substrate is on the second and third transistors. The first and second channels do not directly contact each other, are electrically connected with each other, and receive electrical signals from the second transistor. The first and third transistors apply electrical signals to the first and second gate electrode structures.

Abstract: Provided is a non-volatile memory device including a first structure including a first substrate; a peripheral circuit; a first insulation structure; a plurality of first bonding pads; and a first interconnect structure; a second structure, which includes a conductive etch stop layer; a common source line layer; a stacked structure including alternately stacked gate layers and interlayer insulation layers; a plurality of channel structures penetrating through a cell region of the stacked structure; a second insulation structure; a plurality of second bonding pads; and a second interconnect structure and bonded to the first structure; and a connection layer including a third insulation structure; an input/output via; and an input/output pad, wherein an interface between the second insulation structure and the third insulation structure is disposed at a vertical level between the top surface and the bottom surface of the conductive etch stop layer.