Patents by Inventor Yun-Tack Han

Yun-Tack Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12055968
    Abstract: A semiconductor apparatus includes an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a clock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: August 6, 2024
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Sang Su Lee
  • Patent number: 11942955
    Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Publication number: 20230350452
    Abstract: A semiconductor apparatus includes an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a clock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 2, 2023
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Sang Su LEE
  • Publication number: 20230308103
    Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 28, 2023
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Kyeong Min KIM
  • Patent number: 11750201
    Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Patent number: 11733730
    Abstract: A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: August 22, 2023
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Sang Su Lee
  • Patent number: 11705911
    Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: July 18, 2023
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Patent number: 11695422
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: July 4, 2023
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Publication number: 20230082056
    Abstract: A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.
    Type: Application
    Filed: December 21, 2021
    Publication date: March 16, 2023
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Sang Su LEE
  • Publication number: 20230051365
    Abstract: A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n?1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.
    Type: Application
    Filed: October 28, 2022
    Publication date: February 16, 2023
    Applicant: SK hynix Inc.
    Inventors: Kyeong Min KIM, Yun Tack HAN
  • Patent number: 11558058
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Publication number: 20220052701
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Kyeong Min KIM
  • Publication number: 20220052700
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Kyeong Min KIM
  • Patent number: 11206026
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Publication number: 20210305989
    Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Kyeong Min KIM
  • Patent number: 11100968
    Abstract: A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Seong Ju Lee, Yun Tack Han, Byung Deuk Jeon, Kyu Tae Park
  • Publication number: 20210152166
    Abstract: A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n?1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 20, 2021
    Applicant: SK hynix Inc.
    Inventors: Kyeong Min KIM, Yun Tack HAN
  • Publication number: 20210143807
    Abstract: A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to nth output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n?1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding to delay cell, and a delay amount of the nth delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 13, 2021
    Applicant: SK hynix Inc.
    Inventors: Kyeong Min KIM, Yun Tack HAN
  • Publication number: 20210075429
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Application
    Filed: June 25, 2020
    Publication date: March 11, 2021
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Kyeong Min KIM
  • Publication number: 20210075430
    Abstract: A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.
    Type: Application
    Filed: August 24, 2020
    Publication date: March 11, 2021
    Applicant: SK hynix Inc.
    Inventors: Yun Tack HAN, Kyeong Min KIM