Abstract: A semiconductor device includes a substrate, a first FET part and a second FET part disposed on a surface of the substrate. The first FET part includes a first gate electrode region and a first source electrode region spaced apart from each other. The second FET part, connected to the first FET part in a stacked structure, includes a second gate electrode region and a second drain electrode region spaced apart from each other. Each of the first FET part and the second FET part includes a first common electrode and a second common electrode disposed on the surface of the substrate and spaced apart from each other. Each of the first common electrode and the second common electrode is configured to be a single conductor wiring integrally formed by a first drain electrode of the first FET part and a second source electrode of the second FET part.

Abstract: A semiconductor device includes a substrate, a first FET part and a second FET part disposed on a surface of the substrate. The first FET part includes a first gate electrode region and a first source electrode region spaced apart from each other. The second FET part, connected to the first FET part in a stacked structure, includes a second gate electrode region and a second drain electrode region spaced apart from each other. Each of the first FET part and the second FET part includes a first common electrode and a second common electrode disposed on the surface of the substrate and spaced apart from each other. Each of the first common electrode and the second common electrode is configured to be a single conductor wiring integrally formed by a first drain electrode of the first FET part and a second source electrode of the second FET part.

Abstract: An impedance matching circuit, includes a multilayer substrate, a microstrip line, a spiral inductor, a first capacitor circuit, and a second capacitor circuit. The multilayer substrate includes a power amplifier, and the microstrip line is disposed on a first layer substrate and connected to the power amplifier. The spiral inductor includes a first spiral transmission line disposed on the first layer substrate and connected to the microstrip line, a second spiral transmission line disposed on a substrate layer below the first layer substrate and connected to the first spiral transmission line, and an output pad disposed on the first layer substrate and connected to the second spiral transmission line. The first capacitor circuit is disposed outside the spiral inductor and connected between the microstrip line and a ground. The second capacitor circuit is disposed outside the spiral inductor and connected between the output pad and the ground.

Abstract: An impedance matching circuit, includes a multilayer substrate, a microstrip line, a spiral inductor, a first capacitor circuit, and a second capacitor circuit. The multilayer substrate includes a power amplifier, and the microstrip line is disposed on a first layer substrate and connected to the power amplifier. The spiral inductor includes a first spiral transmission line disposed on the first layer substrate and connected to the microstrip line, a second spiral transmission line disposed on a substrate layer below the first layer substrate and connected to the first spiral transmission line, and an output pad disposed on the first layer substrate and connected to the second spiral transmission line. The first capacitor circuit is disposed outside the spiral inductor and connected between the microstrip line and a ground. The second capacitor circuit is disposed outside the spiral inductor and connected between the output pad and the ground.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a first substrate having an electronic device mounted on both surfaces thereof; and a second substrate bonded to one surface of the first substrate and including an insertion part in which the electronic device mounted on one surface of the first substrate is inserted, wherein the second substrate includes a ground and a shielding wall which is formed along an inner wall or an outer wall of the second substrate.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a first substrate having an electronic device mounted on both surfaces thereof; and a second substrate bonded to one surface of the first substrate and including an insertion part in which the electronic device mounted on one surface of the first substrate is inserted, wherein the second substrate includes a ground and a shielding wall which is formed along an inner wall or an outer wall of the second substrate.