Abstract: A switching device includes a first electrode, a bipolar tunneling layer, and a second electrode. The bipolar tunneling layer is formed on the first electrode and includes a plurality of dielectric layers having different dielectric constants. The second electrode is formed on the bipolar tunneling layer.

Abstract: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region.

Abstract: A switching device includes a first electrode, a bipolar tunneling layer, and a second electrode. The bipolar tunneling layer is formed on the first electrode and includes a plurality of dielectric layers having different dielectric constants. The second electrode is formed on the bipolar tunneling layer.

Abstract: A switching device includes a first electrode, a bipolar tunneling layer, and a second electrode. The bipolar tunneling layer is formed on the first electrode and includes a plurality of dielectric layers having different dielectric constants. The second electrode is formed on the bipolar tunneling layer.

Abstract: A switching device that provides bipolar current paths and a resistance change memory device using the switching device. The switching device includes a first electrode, a second electrode, and an amorphous carbon layer interposed between the first electrode and the second electrode and configured to control a bipolar current to flow therethrough in response to a voltage applied between the first electrode and the second electrode.

Abstract: A resistive memory device includes: a bottom electrode formed over a substrate; and an insulation layer having a hole structure formed over the substrate structure. Herein, the hole structure exposes the bottom electrode, has sidewalls of positive slope, and has a bottom width equal to or smaller than a width of the bottom electrode; a resistive layer formed over the hole structure; and an upper electrode formed over the resistive layer.

Abstract: A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a first silicon layer connected to a first active region of a semiconductor substrate, a second silicon layer and a relaxed silicon germanium layer formed over the first silicon layer expected to be a NMOS region, and a NMOS gate formed over the second silicon layer.

Abstract: A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer.

Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.

Abstract: A switching device includes a first electrode, a bipolar tunneling layer, and a second electrode. The bipolar tunneling layer is formed on the first electrode and includes a plurality of dielectric layers having different dielectric constants. The second electrode is formed on the bipolar tunneling layer.

Abstract: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region.

Abstract: A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer.

Abstract: A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.

Abstract: A resistive memory device and a fabrication method thereof are provided. The fabrication method includes: providing a substrate; forming a lower electrode over the substrate; forming a variable resistive material layer over the lower electrode; forming an ion implantation region to a predetermined depth from a surface of the variable resistive material layer by implanting metal ions or oxygen ions to the surface of the variable resistive material layer; and forming an upper electrode over the variable resistive material layer including the ion implantation region.

Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.

Abstract: A resistance RAM (ReRAM) device and method of manufacturing the same are presented. The ReRAM exhibits an improved set resistance distribution and an improved reset resistance distribution. The ReRAM device includes a lower electrode contact that has at least one carbon nano-tube; and a binary oxide layer formed over the lower electrode contact. The binary oxide layer is for storing information in accordance to two different resistance states of the binary oxide layer.

Abstract: A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a first silicon layer connected to a first active region of a semiconductor substrate, a second silicon layer and a relaxed silicon germanium layer formed over the first silicon layer expected to be a NMOS region, and a NMOS gate formed over the second silicon layer.

Abstract: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance.

Abstract: A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer.